1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018-2021 Marvell International Ltd.
4 */
5
6#include "cn9130-db.dtsi"
7
8/ {
9	model = "Marvell CN9130 development board (CP NOR) setup(A)";
10
11	aliases {
12		spi0 = &cp0_spi1;
13	};
14};
15
16/*
17 * CP related configuration
18 */
19&cp0_pinctl {
20	/* MPP Bus:
21	 *	[0-11]	RGMII1
22	 *	[12]	GPIO GE-IN
23	 *	[13-16]	SPI1
24	 *	[17-27]	NAND
25	 *	[28]	MSS_GPIO[5] XXX:(mode nr from a3900)
26	 *	[29-30]	SATA
27	 *	[31]	MSS_GPIO[4] XXX:(mode nr from a3900)
28	 *	[32,34]	SMI
29	 *	[33]	SDIO
30	 *	[35-36]	I2C1
31	 *	[37-38]	I2C0
32	 *	[39-43]	SDIOctrl
33	 *	[44-55]	RGMII2
34	 *	[56-62]	SDIO
35	 */
36
37		/*   0   1   2   3   4   5   6   7   8   9 */
38	pin-func = < 3   3   3   3   3   3   3   3   3   3
39		     3   3   0   3   3   3   3   1   1   1
40		     1   1   1   1   1   1   1   1   3   9
41		     9   3   7   6   7   2   2   2   2   1
42		     1   1   1   1   1   1   1   1   1   1
43		     1   1   1   1   1   1   0xe 0xe 0xe 0xe
44		     0xe 0xe 0xe>;
45};
46
47/* U54 */
48&cp0_nand {
49	status = "disabled";
50};
51
52/* U55 */
53&cp0_spi1 {
54	status = "okay";
55};
56