1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2019
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
7/dts-v1/;
8#include "imxrt1050.dtsi"
9#include "imxrt1050-evk-u-boot.dtsi"
10#include <dt-bindings/pinctrl/pins-imxrt1050.h>
11
12/ {
13	model = "NXP IMXRT1050-evk board";
14	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
15
16	chosen {
17		bootargs = "root=/dev/ram";
18		stdout-path = "serial0:115200n8";
19		tick-timer = &gpt1;
20	};
21
22	memory {
23		device_type = "memory";
24		reg = <0x80000000 0x2000000>;
25	};
26};
27
28&lpuart1 { /* console */
29	pinctrl-names = "default";
30	pinctrl-0 = <&pinctrl_lpuart1>;
31	status = "okay";
32};
33
34&semc {
35	/*
36	 * Memory configuration from sdram datasheet IS42S16160J-6BLI
37	 */
38	fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
39				MUX_CSX0_SDRAM_CS1
40				0
41				0
42				0
43				0>;
44	fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
45					BL_8
46					COL_9BITS
47					CL_3>;
48	fsl,sdram-timing = /bits/ 8 <0x2
49				     0x2
50				     0x9
51				     0x1
52				     0x5
53				     0x6
54
55				     0x20
56				     0x09
57				     0x01
58				     0x00
59
60				     0x04
61				     0x0A
62				     0x21
63				     0x50>;
64
65	bank1: bank@0 {
66		fsl,base-address = <0x80000000>;
67		fsl,memory-size = <MEM_SIZE_32M>;
68	};
69};
70
71&iomuxc {
72	pinctrl-names = "default";
73	pinctrl-0 = <&pinctrl_lpuart1>;
74
75	imxrt1050-evk {
76		pinctrl_lpuart1: lpuart1grp {
77			fsl,pins = <
78				MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
79					0xf1
80				MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
81					0xf1
82			>;
83		};
84
85		pinctrl_semc: semcgrp {
86			fsl,pins = <
87				MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
88					0xf1	/* SEMC_D0 */
89				MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
90					0xf1	/* SEMC_D1 */
91				MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
92					0xf1	/* SEMC_D2 */
93				MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
94					0xf1	/* SEMC_D3 */
95				MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
96					0xf1	/* SEMC_D4 */
97				MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
98					0xf1	/* SEMC_D5 */
99				MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
100					0xf1	/* SEMC_D6 */
101				MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
102					0xf1	/* SEMC_D7 */
103				MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
104					0xf1	/* SEMC_DM0 */
105				MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
106					0xf1	/* SEMC_A0 */
107				MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
108					0xf1	/* SEMC_A1 */
109				MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
110					0xf1	/* SEMC_A2 */
111				MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
112					0xf1	/* SEMC_A3 */
113				MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
114					0xf1	/* SEMC_A4 */
115				MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
116					0xf1	/* SEMC_A5 */
117				MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
118					0xf1	/* SEMC_A6 */
119				MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
120					0xf1	/* SEMC_A7 */
121				MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
122					0xf1	/* SEMC_A8 */
123				MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
124					0xf1	/* SEMC_A9 */
125				MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
126					0xf1	/* SEMC_A11 */
127				MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
128					0xf1	/* SEMC_A12 */
129				MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
130					0xf1	/* SEMC_BA0 */
131				MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
132					0xf1	/* SEMC_BA1 */
133				MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
134					0xf1	/* SEMC_A10 */
135				MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
136					0xf1	/* SEMC_CAS */
137				MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
138					0xf1	/* SEMC_RAS */
139				MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
140					0xf1	/* SEMC_CLK */
141				MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
142					0xf1	/* SEMC_CKE */
143				MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
144					0xf1	/* SEMC_WE */
145				MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
146					0xf1	/* SEMC_CS0 */
147				MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
148					0xf1	/* SEMC_D8 */
149				MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
150					0xf1	/* SEMC_D9 */
151				MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
152					0xf1	/* SEMC_D10 */
153				MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
154					0xf1	/* SEMC_D11 */
155				MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
156					0xf1	/* SEMC_D12 */
157				MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
158					0xf1	/* SEMC_D13 */
159				MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
160					0xf1	/* SEMC_D14 */
161				MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
162					0xf1	/* SEMC_D15 */
163				MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
164					0xf1	/* SEMC_DM1 */
165				MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
166					(IMX_PAD_SION | 0xf1)	/* SEMC_DQS */
167			>;
168		};
169
170		pinctrl_usdhc0: usdhc0grp {
171			fsl,pins = <
172				MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
173					0x1B000
174				MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
175					0xB069
176				MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
177					0x17061
178				MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
179					0x17061
180				MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
181					0x17061
182				MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
183					0x17061
184				MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
185					0x17061
186				MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
187					0x17061
188			>;
189		};
190
191		pinctrl_lcdif: lcdifgrp {
192			fsl,pins = <
193				MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK		0x1b0b1
194				MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE		0x1b0b1
195				MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC		0x1b0b1
196				MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC		0x1b0b1
197				MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00		0x1b0b1
198				MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01		0x1b0b1
199				MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02		0x1b0b1
200				MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03		0x1b0b1
201				MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04		0x1b0b1
202				MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05		0x1b0b1
203				MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06		0x1b0b1
204				MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07		0x1b0b1
205				MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08		0x1b0b1
206				MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09		0x1b0b1
207				MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10		0x1b0b1
208				MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11		0x1b0b1
209				MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13		0x1b0b1
210				MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14		0x1b0b1
211				MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15		0x1b0b1
212				MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31		0x0b069
213				MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02	0x0b069
214			>;
215		};
216	};
217};
218
219&gpt1 {
220	status = "okay";
221};
222
223&usdhc1 {
224	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
225	pinctrl-0 = <&pinctrl_usdhc0>;
226	pinctrl-1 = <&pinctrl_usdhc0>;
227	pinctrl-2 = <&pinctrl_usdhc0>;
228	pinctrl-3 = <&pinctrl_usdhc0>;
229	status = "okay";
230
231	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
232};
233
234&lcdif {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_lcdif>;
237	display = <&display0>;
238	status = "okay";
239
240	display0: display0 {
241		bits-per-pixel = <16>;
242		bus-width = <16>;
243
244		display-timings {
245			timing0: timing0 {
246				clock-frequency = <9300000>;
247				hactive = <480>;
248				vactive = <272>;
249				hback-porch = <4>;
250				hfront-porch = <8>;
251				vback-porch = <4>;
252				vfront-porch = <8>;
253				hsync-len = <41>;
254				vsync-len = <10>;
255				de-active = <1>;
256				pixelclk-active = <0>;
257				hsync-active = <0>;
258				vsync-active = <0>;
259			};
260		};
261	};
262};
263
264&usbotg1 {
265	dr_mode = "host";
266	status = "okay";
267};
268