1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3308"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 serial4 = &uart4; 31 spi0 = &spi0; 32 spi1 = &spi1; 33 spi2 = &spi2; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35", "arm,armv8"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 clocks = <&cru ARMCLK>; 46 #cooling-cells = <2>; 47 dynamic-power-coefficient = <90>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 cpu-idle-states = <&CPU_SLEEP>; 50 next-level-cache = <&l2>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35", "arm,armv8"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 operating-points-v2 = <&cpu0_opp_table>; 59 cpu-idle-states = <&CPU_SLEEP>; 60 next-level-cache = <&l2>; 61 }; 62 63 cpu2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a35", "arm,armv8"; 66 reg = <0x0 0x2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 cpu-idle-states = <&CPU_SLEEP>; 70 next-level-cache = <&l2>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a35", "arm,armv8"; 76 reg = <0x0 0x3>; 77 enable-method = "psci"; 78 operating-points-v2 = <&cpu0_opp_table>; 79 cpu-idle-states = <&CPU_SLEEP>; 80 next-level-cache = <&l2>; 81 }; 82 83 idle-states { 84 entry-method = "psci"; 85 86 CPU_SLEEP: cpu-sleep { 87 compatible = "arm,idle-state"; 88 local-timer-stop; 89 arm,psci-suspend-param = <0x0010000>; 90 entry-latency-us = <120>; 91 exit-latency-us = <250>; 92 min-residency-us = <900>; 93 }; 94 }; 95 96 l2: l2-cache { 97 compatible = "cache"; 98 }; 99 }; 100 101 cpu0_opp_table: cpu0-opp-table { 102 compatible = "operating-points-v2"; 103 opp-shared; 104 105 opp-408000000 { 106 opp-hz = /bits/ 64 <408000000>; 107 opp-microvolt = <950000 950000 1340000>; 108 clock-latency-ns = <40000>; 109 opp-suspend; 110 }; 111 opp-600000000 { 112 opp-hz = /bits/ 64 <600000000>; 113 opp-microvolt = <950000 950000 1340000>; 114 clock-latency-ns = <40000>; 115 }; 116 opp-816000000 { 117 opp-hz = /bits/ 64 <816000000>; 118 opp-microvolt = <1025000 1025000 1340000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1008000000 { 122 opp-hz = /bits/ 64 <1008000000>; 123 opp-microvolt = <1125000 1125000 1340000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 arm-pmu { 129 compatible = "arm,cortex-a53-pmu"; 130 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 134 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 135 }; 136 137 mac_clkin: external-mac-clock { 138 compatible = "fixed-clock"; 139 clock-frequency = <50000000>; 140 clock-output-names = "mac_clkin"; 141 #clock-cells = <0>; 142 }; 143 144 psci { 145 compatible = "arm,psci-1.0"; 146 method = "smc"; 147 }; 148 149 timer { 150 compatible = "arm,armv8-timer"; 151 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 152 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 153 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 155 }; 156 157 xin24m: xin24m { 158 compatible = "fixed-clock"; 159 #clock-cells = <0>; 160 clock-frequency = <24000000>; 161 clock-output-names = "xin24m"; 162 }; 163 164 grf: grf@ff000000 { 165 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 166 reg = <0x0 0xff000000 0x0 0x10000>; 167 }; 168 169 dmc: dmc@0xff010000 { 170 compatible = "rockchip,rk3308-dmc"; 171 reg = <0x0 0xff010000 0x0 0x10000>; 172 }; 173 174 detect_grf: syscon@ff00b000 { 175 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 176 reg = <0x0 0xff00b000 0x0 0x1000>; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 }; 180 181 core_grf: syscon@ff00c000 { 182 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 183 reg = <0x0 0xff00c000 0x0 0x1000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 187 }; 188 189 i2c0: i2c@ff040000 { 190 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 191 reg = <0x0 0xff040000 0x0 0x1000>; 192 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 193 clock-names = "i2c", "pclk"; 194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&i2c0_xfer>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 status = "disabled"; 200 }; 201 202 i2c1: i2c@ff050000 { 203 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 204 reg = <0x0 0xff050000 0x0 0x1000>; 205 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 206 clock-names = "i2c", "pclk"; 207 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&i2c1_xfer>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 status = "disabled"; 213 }; 214 215 i2c2: i2c@ff060000 { 216 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 217 reg = <0x0 0xff060000 0x0 0x1000>; 218 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 219 clock-names = "i2c", "pclk"; 220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&i2c2_xfer>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 status = "disabled"; 226 }; 227 228 i2c3: i2c@ff070000 { 229 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 230 reg = <0x0 0xff070000 0x0 0x1000>; 231 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 232 clock-names = "i2c", "pclk"; 233 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&i2c3m0_xfer>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 status = "disabled"; 239 }; 240 241 wdt: watchdog@ff080000 { 242 compatible = "snps,dw-wdt"; 243 reg = <0x0 0xff080000 0x0 0x100>; 244 clocks = <&cru PCLK_WDT>; 245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 246 status = "disabled"; 247 }; 248 249 uart0: serial@ff0a0000 { 250 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 251 reg = <0x0 0xff0a0000 0x0 0x100>; 252 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 254 clock-names = "baudclk", "apb_pclk"; 255 reg-shift = <2>; 256 reg-io-width = <4>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 259 status = "disabled"; 260 }; 261 262 uart1: serial@ff0b0000 { 263 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 264 reg = <0x0 0xff0b0000 0x0 0x100>; 265 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 267 clock-names = "baudclk", "apb_pclk"; 268 reg-shift = <2>; 269 reg-io-width = <4>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 272 status = "disabled"; 273 }; 274 275 uart2: serial@ff0c0000 { 276 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 277 reg = <0x0 0xff0c0000 0x0 0x100>; 278 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 280 clock-names = "baudclk", "apb_pclk"; 281 reg-shift = <2>; 282 reg-io-width = <4>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&uart2m0_xfer>; 285 status = "disabled"; 286 }; 287 288 uart3: serial@ff0d0000 { 289 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 290 reg = <0x0 0xff0d0000 0x0 0x100>; 291 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 293 clock-names = "baudclk", "apb_pclk"; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&uart3_xfer>; 298 status = "disabled"; 299 }; 300 301 uart4: serial@ff0e0000 { 302 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 303 reg = <0x0 0xff0e0000 0x0 0x100>; 304 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 306 clock-names = "baudclk", "apb_pclk"; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 311 status = "disabled"; 312 }; 313 314 spi0: spi@ff120000 { 315 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 316 reg = <0x0 0xff120000 0x0 0x1000>; 317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 321 clock-names = "spiclk", "apb_pclk"; 322 dmas = <&dmac0 0>, <&dmac0 1>; 323 dma-names = "tx", "rx"; 324 pinctrl-names = "default", "high_speed"; 325 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 326 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; 327 status = "disabled"; 328 }; 329 330 spi1: spi@ff130000 { 331 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 332 reg = <0x0 0xff130000 0x0 0x1000>; 333 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 337 clock-names = "spiclk", "apb_pclk"; 338 dmas = <&dmac0 2>, <&dmac0 3>; 339 dma-names = "tx", "rx"; 340 pinctrl-names = "default", "high_speed"; 341 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 342 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>; 343 status = "disabled"; 344 }; 345 346 spi2: spi@ff140000 { 347 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 348 reg = <0x0 0xff140000 0x0 0x1000>; 349 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 353 clock-names = "spiclk", "apb_pclk"; 354 dmas = <&dmac1 16>, <&dmac1 17>; 355 dma-names = "tx", "rx"; 356 pinctrl-names = "default", "high_speed"; 357 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 358 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; 359 status = "disabled"; 360 }; 361 362 pwm8: pwm@ff160000 { 363 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 364 reg = <0x0 0xff160000 0x0 0x10>; 365 #pwm-cells = <3>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pwm8_pin>; 368 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 369 clock-names = "pwm", "pclk"; 370 status = "disabled"; 371 }; 372 373 pwm9: pwm@ff160010 { 374 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 375 reg = <0x0 0xff160010 0x0 0x10>; 376 #pwm-cells = <3>; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pwm9_pin>; 379 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 380 clock-names = "pwm", "pclk"; 381 status = "disabled"; 382 }; 383 384 pwm10: pwm@ff160020 { 385 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 386 reg = <0x0 0xff160020 0x0 0x10>; 387 #pwm-cells = <3>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pwm10_pin>; 390 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 391 clock-names = "pwm", "pclk"; 392 status = "disabled"; 393 }; 394 395 pwm11: pwm@ff160030 { 396 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 397 reg = <0x0 0xff160030 0x0 0x10>; 398 #pwm-cells = <3>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pwm11_pin>; 401 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 402 clock-names = "pwm", "pclk"; 403 status = "disabled"; 404 }; 405 406 pwm4: pwm@ff170000 { 407 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 408 reg = <0x0 0xff170000 0x0 0x10>; 409 #pwm-cells = <3>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pwm4_pin>; 412 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 413 clock-names = "pwm", "pclk"; 414 status = "disabled"; 415 }; 416 417 pwm5: pwm@ff170010 { 418 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 419 reg = <0x0 0xff170010 0x0 0x10>; 420 #pwm-cells = <3>; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pwm5_pin>; 423 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 424 clock-names = "pwm", "pclk"; 425 status = "disabled"; 426 }; 427 428 pwm6: pwm@ff170020 { 429 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 430 reg = <0x0 0xff170020 0x0 0x10>; 431 #pwm-cells = <3>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pwm6_pin>; 434 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 435 clock-names = "pwm", "pclk"; 436 status = "disabled"; 437 }; 438 439 pwm7: pwm@ff170030 { 440 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 441 reg = <0x0 0xff170030 0x0 0x10>; 442 #pwm-cells = <3>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pwm7_pin>; 445 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 446 clock-names = "pwm", "pclk"; 447 status = "disabled"; 448 }; 449 450 pwm0: pwm@ff180000 { 451 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 452 reg = <0x0 0xff180000 0x0 0x10>; 453 #pwm-cells = <3>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&pwm0_pin>; 456 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 457 clock-names = "pwm", "pclk"; 458 status = "disabled"; 459 }; 460 461 pwm1: pwm@ff180010 { 462 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 463 reg = <0x0 0xff180010 0x0 0x10>; 464 #pwm-cells = <3>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pwm1_pin>; 467 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 468 clock-names = "pwm", "pclk"; 469 status = "disabled"; 470 }; 471 472 pwm2: pwm@ff180020 { 473 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 474 reg = <0x0 0xff180020 0x0 0x10>; 475 #pwm-cells = <3>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pwm2_pin>; 478 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 479 clock-names = "pwm", "pclk"; 480 status = "disabled"; 481 }; 482 483 pwm3: pwm@ff180030 { 484 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 485 reg = <0x0 0xff180030 0x0 0x10>; 486 #pwm-cells = <3>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pwm3_pin>; 489 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 490 clock-names = "pwm", "pclk"; 491 status = "disabled"; 492 }; 493 494 rktimer: rktimer@ff1a0000 { 495 compatible = "rockchip,rk3288-timer"; 496 reg = <0x0 0xff1a0000 0x0 0x20>; 497 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 499 clock-names = "pclk", "timer"; 500 }; 501 502 saradc: saradc@ff1e0000 { 503 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 504 reg = <0x0 0xff1e0000 0x0 0x100>; 505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 506 #io-channel-cells = <1>; 507 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 508 clock-names = "saradc", "apb_pclk"; 509 resets = <&cru SRST_SARADC_P>; 510 reset-names = "saradc-apb"; 511 status = "disabled"; 512 }; 513 514 amba { 515 compatible = "arm,amba-bus"; 516 #address-cells = <2>; 517 #size-cells = <2>; 518 ranges; 519 520 dmac0: dma-controller@ff2c0000 { 521 compatible = "arm,pl330", "arm,primecell"; 522 reg = <0x0 0xff2c0000 0x0 0x4000>; 523 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 525 #dma-cells = <1>; 526 clocks = <&cru ACLK_DMAC0>; 527 clock-names = "apb_pclk"; 528 peripherals-req-type-burst; 529 }; 530 531 dmac1: dma-controller@ff2d0000 { 532 compatible = "arm,pl330", "arm,primecell"; 533 reg = <0x0 0xff2d0000 0x0 0x4000>; 534 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 536 #dma-cells = <1>; 537 clocks = <&cru ACLK_DMAC1>; 538 clock-names = "apb_pclk"; 539 peripherals-req-type-burst; 540 }; 541 }; 542 543 i2s_2ch_0: i2s@ff350000 { 544 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 545 reg = <0x0 0xff350000 0x0 0x1000>; 546 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 548 clock-names = "i2s_clk", "i2s_hclk"; 549 dmas = <&dmac1 8>, <&dmac1 9>; 550 dma-names = "tx", "rx"; 551 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 552 reset-names = "reset-m", "reset-h"; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&i2s_2ch_0_sclk 555 &i2s_2ch_0_lrck 556 &i2s_2ch_0_sdi 557 &i2s_2ch_0_sdo>; 558 status = "disabled"; 559 }; 560 561 i2s_2ch_1: i2s@ff360000 { 562 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 563 reg = <0x0 0xff360000 0x0 0x1000>; 564 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 566 clock-names = "i2s_clk", "i2s_hclk"; 567 dmas = <&dmac1 11>; 568 dma-names = "rx"; 569 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 570 reset-names = "reset-m", "reset-h"; 571 status = "disabled"; 572 }; 573 574 spdif_tx: spdif-tx@ff3a0000 { 575 compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif"; 576 reg = <0x0 0xff3a0000 0x0 0x1000>; 577 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 579 clock-names = "mclk", "hclk"; 580 dmas = <&dmac1 13>; 581 dma-names = "tx"; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&spdif_out>; 584 status = "disabled"; 585 }; 586 587 sdmmc: dwmmc@ff480000 { 588 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 589 reg = <0x0 0xff480000 0x0 0x4000>; 590 max-frequency = <150000000>; 591 bus-width = <4>; 592 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 593 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 594 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 595 fifo-depth = <0x100>; 596 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 599 status = "disabled"; 600 }; 601 602 emmc: dwmmc@ff490000 { 603 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 604 reg = <0x0 0xff490000 0x0 0x4000>; 605 max-frequency = <150000000>; 606 bus-width = <8>; 607 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 608 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 609 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 610 fifo-depth = <0x100>; 611 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 }; 614 615 sdio: dwmmc@ff4a0000 { 616 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 617 reg = <0x0 0xff4a0000 0x0 0x4000>; 618 max-frequency = <150000000>; 619 bus-width = <4>; 620 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 621 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 622 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 623 fifo-depth = <0x100>; 624 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 627 status = "disabled"; 628 }; 629 630 mac: ethernet@ff4e0000 { 631 compatible = "rockchip,rk3308-mac"; 632 reg = <0x0 0xff4e0000 0x0 0x10000>; 633 rockchip,grf = <&grf>; 634 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 635 interrupt-names = "macirq"; 636 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 637 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 638 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 639 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 640 clock-names = "stmmaceth", "mac_clk_rx", 641 "mac_clk_tx", "clk_mac_ref", 642 "clk_mac_refout", "aclk_mac", 643 "pclk_mac", "clk_mac_speed"; 644 phy-mode = "rmii"; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 647 resets = <&cru SRST_MAC_A>; 648 reset-names = "stmmaceth"; 649 status = "disabled"; 650 }; 651 652 cru: clock-controller@ff500000 { 653 compatible = "rockchip,rk3308-cru"; 654 reg = <0x0 0xff500000 0x0 0x1000>; 655 rockchip,grf = <&grf>; 656 #clock-cells = <1>; 657 #reset-cells = <1>; 658 }; 659 660 gic: interrupt-controller@ff580000 { 661 compatible = "arm,gic-400"; 662 #interrupt-cells = <3>; 663 #address-cells = <0>; 664 interrupt-controller; 665 666 reg = <0x0 0xff581000 0x0 0x1000>, 667 <0x0 0xff582000 0x0 0x2000>, 668 <0x0 0xff584000 0x0 0x2000>, 669 <0x0 0xff586000 0x0 0x2000>; 670 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 671 }; 672 673 sram: sram@fff80000 { 674 compatible = "mmio-sram"; 675 reg = <0x0 0xfff80000 0x0 0x40000>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges = <0 0x0 0xfff80000 0x40000>; 679 /* reserved for ddr dvfs and system suspend/resume */ 680 ddr-sram@0 { 681 reg = <0x0 0x8000>; 682 }; 683 /* reserved for vad audio buffer */ 684 vad_sram: vad-sram@8000 { 685 reg = <0x8000 0x38000>; 686 }; 687 }; 688 689 pinctrl: pinctrl { 690 compatible = "rockchip,rk3308-pinctrl"; 691 rockchip,grf = <&grf>; 692 #address-cells = <2>; 693 #size-cells = <2>; 694 ranges; 695 gpio0: gpio0@ff220000 { 696 compatible = "rockchip,gpio-bank"; 697 reg = <0x0 0xff220000 0x0 0x100>; 698 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru PCLK_GPIO0>; 700 gpio-controller; 701 #gpio-cells = <2>; 702 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 707 gpio1: gpio1@ff230000 { 708 compatible = "rockchip,gpio-bank"; 709 reg = <0x0 0xff230000 0x0 0x100>; 710 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cru PCLK_GPIO1>; 712 gpio-controller; 713 #gpio-cells = <2>; 714 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 gpio2: gpio2@ff240000 { 720 compatible = "rockchip,gpio-bank"; 721 reg = <0x0 0xff240000 0x0 0x100>; 722 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&cru PCLK_GPIO2>; 724 gpio-controller; 725 #gpio-cells = <2>; 726 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 731 gpio3: gpio3@ff250000 { 732 compatible = "rockchip,gpio-bank"; 733 reg = <0x0 0xff250000 0x0 0x100>; 734 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&cru PCLK_GPIO3>; 736 gpio-controller; 737 #gpio-cells = <2>; 738 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 743 gpio4: gpio4@ff260000 { 744 compatible = "rockchip,gpio-bank"; 745 reg = <0x0 0xff260000 0x0 0x100>; 746 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cru PCLK_GPIO4>; 748 gpio-controller; 749 #gpio-cells = <2>; 750 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 }; 754 755 pcfg_pull_up: pcfg-pull-up { 756 bias-pull-up; 757 }; 758 759 pcfg_pull_down: pcfg-pull-down { 760 bias-pull-down; 761 }; 762 763 pcfg_pull_none: pcfg-pull-none { 764 bias-disable; 765 }; 766 767 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 768 bias-disable; 769 drive-strength = <2>; 770 }; 771 772 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 773 bias-pull-up; 774 drive-strength = <2>; 775 }; 776 777 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 778 bias-pull-up; 779 drive-strength = <4>; 780 }; 781 782 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 783 bias-disable; 784 drive-strength = <4>; 785 }; 786 787 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 788 bias-pull-down; 789 drive-strength = <4>; 790 }; 791 792 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 793 bias-disable; 794 drive-strength = <8>; 795 }; 796 797 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 798 bias-pull-up; 799 drive-strength = <8>; 800 }; 801 802 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 803 bias-disable; 804 drive-strength = <12>; 805 }; 806 807 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 808 bias-pull-up; 809 drive-strength = <12>; 810 }; 811 812 pcfg_pull_none_smt: pcfg-pull-none-smt { 813 bias-disable; 814 input-schmitt-enable; 815 }; 816 817 pcfg_output_high: pcfg-output-high { 818 output-high; 819 }; 820 821 pcfg_output_low: pcfg-output-low { 822 output-low; 823 }; 824 825 pcfg_input_high: pcfg-input-high { 826 bias-pull-up; 827 input-enable; 828 }; 829 830 pcfg_input: pcfg-input { 831 input-enable; 832 }; 833 834 i2c0 { 835 i2c0_xfer: i2c0-xfer { 836 rockchip,pins = 837 <1 RK_PD0 2 &pcfg_pull_none_smt>, 838 <1 RK_PD1 2 &pcfg_pull_none_smt>; 839 }; 840 }; 841 842 i2c1 { 843 i2c1_xfer: i2c1-xfer { 844 rockchip,pins = 845 <0 RK_PB3 1 &pcfg_pull_none_smt>, 846 <0 RK_PB4 1 &pcfg_pull_none_smt>; 847 }; 848 }; 849 850 i2c2 { 851 i2c2_xfer: i2c2-xfer { 852 rockchip,pins = 853 <2 RK_PA2 3 &pcfg_pull_none_smt>, 854 <2 RK_PA3 3 &pcfg_pull_none_smt>; 855 }; 856 }; 857 858 i2c3-m0 { 859 i2c3m0_xfer: i2c3m0-xfer { 860 rockchip,pins = 861 <0 RK_PB7 2 &pcfg_pull_none_smt>, 862 <0 RK_PC0 2 &pcfg_pull_none_smt>; 863 }; 864 }; 865 866 i2c3-m1 { 867 i2c3m1_xfer: i2c3m1-xfer { 868 rockchip,pins = 869 <3 RK_PB4 2 &pcfg_pull_none_smt>, 870 <3 RK_PB5 2 &pcfg_pull_none_smt>; 871 }; 872 }; 873 874 i2c3-m2 { 875 i2c3m2_xfer: i2c3m2-xfer { 876 rockchip,pins = 877 <2 RK_PA1 3 &pcfg_pull_none_smt>, 878 <2 RK_PA0 3 &pcfg_pull_none_smt>; 879 }; 880 }; 881 882 i2s_2ch_0 { 883 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 884 rockchip,pins = 885 <4 RK_PB4 1 &pcfg_pull_none>; 886 }; 887 888 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 889 rockchip,pins = 890 <4 RK_PB5 1 &pcfg_pull_none>; 891 }; 892 893 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 894 rockchip,pins = 895 <4 RK_PB6 1 &pcfg_pull_none>; 896 }; 897 898 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 899 rockchip,pins = 900 <4 RK_PB7 1 &pcfg_pull_none>; 901 }; 902 903 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 904 rockchip,pins = 905 <4 RK_PC0 1 &pcfg_pull_none>; 906 }; 907 }; 908 909 i2s_8ch_0 { 910 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 911 rockchip,pins = 912 <2 RK_PA4 1 &pcfg_pull_none>; 913 }; 914 915 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 916 rockchip,pins = 917 <2 RK_PA5 1 &pcfg_pull_none>; 918 }; 919 920 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 921 rockchip,pins = 922 <2 RK_PA6 1 &pcfg_pull_none>; 923 }; 924 925 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 926 rockchip,pins = 927 <2 RK_PA7 1 &pcfg_pull_none>; 928 }; 929 930 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 931 rockchip,pins = 932 <2 RK_PB0 1 &pcfg_pull_none>; 933 }; 934 935 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 936 rockchip,pins = 937 <2 RK_PB1 1 &pcfg_pull_none>; 938 }; 939 940 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 941 rockchip,pins = 942 <2 RK_PB2 1 &pcfg_pull_none>; 943 }; 944 945 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 946 rockchip,pins = 947 <2 RK_PB3 1 &pcfg_pull_none>; 948 }; 949 950 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 951 rockchip,pins = 952 <2 RK_PB4 1 &pcfg_pull_none>; 953 }; 954 955 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 956 rockchip,pins = 957 <2 RK_PB5 1 &pcfg_pull_none>; 958 }; 959 960 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 961 rockchip,pins = 962 <2 RK_PB6 1 &pcfg_pull_none>; 963 }; 964 965 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 966 rockchip,pins = 967 <2 RK_PB7 1 &pcfg_pull_none>; 968 }; 969 970 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 971 rockchip,pins = 972 <2 RK_PC0 1 &pcfg_pull_none>; 973 }; 974 }; 975 976 i2s_8ch_1_m0 { 977 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 978 rockchip,pins = 979 <1 RK_PA2 2 &pcfg_pull_none>; 980 }; 981 982 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 983 rockchip,pins = 984 <1 RK_PA3 2 &pcfg_pull_none>; 985 }; 986 987 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 988 rockchip,pins = 989 <1 RK_PA4 2 &pcfg_pull_none>; 990 }; 991 992 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 993 rockchip,pins = 994 <1 RK_PA5 2 &pcfg_pull_none>; 995 }; 996 997 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 998 rockchip,pins = 999 <1 RK_PA6 2 &pcfg_pull_none>; 1000 }; 1001 1002 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1003 rockchip,pins = 1004 <1 RK_PA7 2 &pcfg_pull_none>; 1005 }; 1006 1007 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1008 rockchip,pins = 1009 <1 RK_PB0 2 &pcfg_pull_none>; 1010 }; 1011 1012 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1013 rockchip,pins = 1014 <1 RK_PB1 2 &pcfg_pull_none>; 1015 }; 1016 1017 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1018 rockchip,pins = 1019 <1 RK_PB2 2 &pcfg_pull_none>; 1020 }; 1021 1022 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1023 rockchip,pins = 1024 <1 RK_PB3 2 &pcfg_pull_none>; 1025 }; 1026 }; 1027 1028 i2s_8ch_1_m1 { 1029 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1030 rockchip,pins = 1031 <1 RK_PB4 2 &pcfg_pull_none>; 1032 }; 1033 1034 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1035 rockchip,pins = 1036 <1 RK_PB5 2 &pcfg_pull_none>; 1037 }; 1038 1039 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1040 rockchip,pins = 1041 <1 RK_PB6 2 &pcfg_pull_none>; 1042 }; 1043 1044 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1045 rockchip,pins = 1046 <1 RK_PB7 2 &pcfg_pull_none>; 1047 }; 1048 1049 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1050 rockchip,pins = 1051 <1 RK_PC0 2 &pcfg_pull_none>; 1052 }; 1053 1054 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1055 rockchip,pins = 1056 <1 RK_PC1 2 &pcfg_pull_none>; 1057 }; 1058 1059 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1060 rockchip,pins = 1061 <1 RK_PC2 2 &pcfg_pull_none>; 1062 }; 1063 1064 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1065 rockchip,pins = 1066 <1 RK_PC3 2 &pcfg_pull_none>; 1067 }; 1068 1069 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1070 rockchip,pins = 1071 <1 RK_PC4 2 &pcfg_pull_none>; 1072 }; 1073 1074 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1075 rockchip,pins = 1076 <1 RK_PC5 2 &pcfg_pull_none>; 1077 }; 1078 }; 1079 1080 pdm_m0 { 1081 pdm_m0_clk: pdm-m0-clk { 1082 rockchip,pins = 1083 <1 RK_PA4 3 &pcfg_pull_none>; 1084 }; 1085 1086 pdm_m0_sdi0: pdm-m0-sdi0 { 1087 rockchip,pins = 1088 <1 RK_PB3 3 &pcfg_pull_none>; 1089 }; 1090 1091 pdm_m0_sdi1: pdm-m0-sdi1 { 1092 rockchip,pins = 1093 <1 RK_PB2 3 &pcfg_pull_none>; 1094 }; 1095 1096 pdm_m0_sdi2: pdm-m0-sdi2 { 1097 rockchip,pins = 1098 <1 RK_PB1 3 &pcfg_pull_none>; 1099 }; 1100 1101 pdm_m0_sdi3: pdm-m0-sdi3 { 1102 rockchip,pins = 1103 <1 RK_PB0 3 &pcfg_pull_none>; 1104 }; 1105 }; 1106 1107 pdm_m1 { 1108 pdm_m1_clk: pdm-m1-clk { 1109 rockchip,pins = 1110 <1 RK_PB6 4 &pcfg_pull_none>; 1111 }; 1112 1113 pdm_m1_sdi0: pdm-m1-sdi0 { 1114 rockchip,pins = 1115 <1 RK_PC5 4 &pcfg_pull_none>; 1116 }; 1117 1118 pdm_m1_sdi1: pdm-m1-sdi1 { 1119 rockchip,pins = 1120 <1 RK_PC4 4 &pcfg_pull_none>; 1121 }; 1122 1123 pdm_m1_sdi2: pdm-m1-sdi2 { 1124 rockchip,pins = 1125 <1 RK_PC3 4 &pcfg_pull_none>; 1126 }; 1127 1128 pdm_m1_sdi3: pdm-m1-sdi3 { 1129 rockchip,pins = 1130 <1 RK_PC2 4 &pcfg_pull_none>; 1131 }; 1132 }; 1133 1134 pdm_m2 { 1135 pdm_m2_clkm: pdm-m2-clkm { 1136 rockchip,pins = 1137 <2 RK_PA4 3 &pcfg_pull_none>; 1138 }; 1139 1140 pdm_m2_clk: pdm-m2-clk { 1141 rockchip,pins = 1142 <2 RK_PA6 2 &pcfg_pull_none>; 1143 }; 1144 1145 pdm_m2_sdi0: pdm-m2-sdi0 { 1146 rockchip,pins = 1147 <2 RK_PB5 2 &pcfg_pull_none>; 1148 }; 1149 1150 pdm_m2_sdi1: pdm-m2-sdi1 { 1151 rockchip,pins = 1152 <2 RK_PB6 2 &pcfg_pull_none>; 1153 }; 1154 1155 pdm_m2_sdi2: pdm-m2-sdi2 { 1156 rockchip,pins = 1157 <2 RK_PB7 2 &pcfg_pull_none>; 1158 }; 1159 1160 pdm_m2_sdi3: pdm-m2-sdi3 { 1161 rockchip,pins = 1162 <2 RK_PC0 2 &pcfg_pull_none>; 1163 }; 1164 }; 1165 1166 spdif_in { 1167 spdif_in: spdif-in { 1168 rockchip,pins = 1169 <0 RK_PC2 1 &pcfg_pull_none>; 1170 }; 1171 }; 1172 1173 spdif_out { 1174 spdif_out: spdif-out { 1175 rockchip,pins = 1176 <0 RK_PC1 1 &pcfg_pull_none>; 1177 }; 1178 }; 1179 1180 tsadc { 1181 tsadc_otp_gpio: tsadc-otp-gpio { 1182 rockchip,pins = 1183 <0 RK_PB2 0 &pcfg_pull_none>; 1184 }; 1185 1186 tsadc_otp_out: tsadc-otp-out { 1187 rockchip,pins = 1188 <0 RK_PB2 1 &pcfg_pull_none>; 1189 }; 1190 }; 1191 1192 uart0 { 1193 uart0_xfer: uart0-xfer { 1194 rockchip,pins = 1195 <2 RK_PA1 1 &pcfg_pull_up>, 1196 <2 RK_PA0 1 &pcfg_pull_up>; 1197 }; 1198 1199 uart0_cts: uart0-cts { 1200 rockchip,pins = 1201 <2 RK_PA2 1 &pcfg_pull_none>; 1202 }; 1203 1204 uart0_rts: uart0-rts { 1205 rockchip,pins = 1206 <2 RK_PA3 1 &pcfg_pull_none>; 1207 }; 1208 1209 uart0_rts_gpio: uart0-rts-gpio { 1210 rockchip,pins = 1211 <2 RK_PA3 0 &pcfg_pull_none>; 1212 }; 1213 }; 1214 1215 uart1 { 1216 uart1_xfer: uart1-xfer { 1217 rockchip,pins = 1218 <1 RK_PD1 1 &pcfg_pull_up>, 1219 <1 RK_PD0 1 &pcfg_pull_up>; 1220 }; 1221 1222 uart1_cts: uart1-cts { 1223 rockchip,pins = 1224 <1 RK_PC6 1 &pcfg_pull_none>; 1225 }; 1226 1227 uart1_rts: uart1-rts { 1228 rockchip,pins = 1229 <1 RK_PC7 1 &pcfg_pull_none>; 1230 }; 1231 }; 1232 1233 uart2-m0 { 1234 uart2m0_xfer: uart2m0-xfer { 1235 rockchip,pins = 1236 <1 RK_PC7 2 &pcfg_pull_up>, 1237 <1 RK_PC6 2 &pcfg_pull_up>; 1238 }; 1239 }; 1240 1241 uart2-m1 { 1242 uart2m1_xfer: uart2m1-xfer { 1243 rockchip,pins = 1244 <4 RK_PD3 2 &pcfg_pull_up>, 1245 <4 RK_PD2 2 &pcfg_pull_up>; 1246 }; 1247 }; 1248 1249 uart3 { 1250 uart3_xfer: uart3-xfer { 1251 rockchip,pins = 1252 <3 RK_PB5 4 &pcfg_pull_up>, 1253 <3 RK_PB4 4 &pcfg_pull_up>; 1254 }; 1255 }; 1256 1257 uart3-m1 { 1258 uart3m1_xfer: uart3m1-xfer { 1259 rockchip,pins = 1260 <0 RK_PC2 3 &pcfg_pull_up>, 1261 <0 RK_PC1 3 &pcfg_pull_up>; 1262 }; 1263 }; 1264 1265 uart4 { 1266 1267 uart4_xfer: uart4-xfer { 1268 rockchip,pins = 1269 <4 RK_PB1 1 &pcfg_pull_up>, 1270 <4 RK_PB0 1 &pcfg_pull_up>; 1271 }; 1272 1273 uart4_cts: uart4-cts { 1274 rockchip,pins = 1275 <4 RK_PA6 1 &pcfg_pull_none>; 1276 1277 }; 1278 1279 uart4_rts: uart4-rts { 1280 rockchip,pins = 1281 <4 RK_PA7 1 &pcfg_pull_none>; 1282 }; 1283 1284 uart4_rts_gpio: uart4-rts-gpio { 1285 rockchip,pins = 1286 <4 RK_PA7 0 &pcfg_pull_none>; 1287 }; 1288 }; 1289 1290 spi0 { 1291 spi0_clk: spi0-clk { 1292 rockchip,pins = 1293 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1294 }; 1295 1296 spi0_csn0: spi0-csn0 { 1297 rockchip,pins = 1298 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1299 }; 1300 1301 spi0_miso: spi0-miso { 1302 rockchip,pins = 1303 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1304 }; 1305 1306 spi0_mosi: spi0-mosi { 1307 rockchip,pins = 1308 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1309 }; 1310 1311 spi0_clk_hs: spi0-clk-hs { 1312 rockchip,pins = 1313 <2 RK_PA2 2 &pcfg_pull_up_8ma>; 1314 }; 1315 1316 spi0_miso_hs: spi0-miso-hs { 1317 rockchip,pins = 1318 <2 RK_PA0 2 &pcfg_pull_up_8ma>; 1319 }; 1320 1321 spi0_mosi_hs: spi0-mosi-hs { 1322 rockchip,pins = 1323 <2 RK_PA1 2 &pcfg_pull_up_8ma>; 1324 }; 1325 1326 }; 1327 1328 spi1 { 1329 spi1_clk: spi1-clk { 1330 rockchip,pins = 1331 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1332 }; 1333 1334 spi1_csn0: spi1-csn0 { 1335 rockchip,pins = 1336 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1337 }; 1338 1339 spi1_miso: spi1-miso { 1340 rockchip,pins = 1341 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1342 }; 1343 1344 spi1_mosi: spi1-mosi { 1345 rockchip,pins = 1346 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1347 }; 1348 1349 spi1_clk_hs: spi1-clk-hs { 1350 rockchip,pins = 1351 <3 RK_PB3 3 &pcfg_pull_up_8ma>; 1352 }; 1353 1354 spi1_miso_hs: spi1-miso-hs { 1355 rockchip,pins = 1356 <3 RK_PB2 3 &pcfg_pull_up_8ma>; 1357 }; 1358 1359 spi1_mosi_hs: spi1-mosi-hs { 1360 rockchip,pins = 1361 <3 RK_PB4 3 &pcfg_pull_up_8ma>; 1362 }; 1363 }; 1364 1365 spi1-m1 { 1366 spi1m1_miso: spi1m1-miso { 1367 rockchip,pins = 1368 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1369 }; 1370 1371 spi1m1_mosi: spi1m1-mosi { 1372 rockchip,pins = 1373 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1374 }; 1375 1376 spi1m1_clk: spi1m1-clk { 1377 rockchip,pins = 1378 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1379 }; 1380 1381 spi1m1_csn0: spi1m1-csn0 { 1382 rockchip,pins = 1383 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1384 }; 1385 1386 spi1m1_miso_hs: spi1m1-miso-hs { 1387 rockchip,pins = 1388 <2 RK_PA4 2 &pcfg_pull_up_8ma>; 1389 }; 1390 1391 spi1m1_mosi_hs: spi1m1-mosi-hs { 1392 rockchip,pins = 1393 <2 RK_PA5 2 &pcfg_pull_up_8ma>; 1394 }; 1395 1396 spi1m1_clk_hs: spi1m1-clk-hs { 1397 rockchip,pins = 1398 <2 RK_PA7 2 &pcfg_pull_up_8ma>; 1399 }; 1400 1401 spi1m1_csn0_hs: spi1m1-csn0-hs { 1402 rockchip,pins = 1403 <2 RK_PB1 2 &pcfg_pull_up_8ma>; 1404 }; 1405 }; 1406 1407 spi2 { 1408 spi2_clk: spi2-clk { 1409 rockchip,pins = 1410 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1411 }; 1412 1413 spi2_csn0: spi2-csn0 { 1414 rockchip,pins = 1415 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1416 }; 1417 1418 spi2_miso: spi2-miso { 1419 rockchip,pins = 1420 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1421 }; 1422 1423 spi2_mosi: spi2-mosi { 1424 rockchip,pins = 1425 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1426 }; 1427 1428 spi2_clk_hs: spi2-clk-hs { 1429 rockchip,pins = 1430 <1 RK_PD0 3 &pcfg_pull_up_8ma>; 1431 }; 1432 1433 spi2_miso_hs: spi2-miso-hs { 1434 rockchip,pins = 1435 <1 RK_PC6 3 &pcfg_pull_up_8ma>; 1436 }; 1437 1438 spi2_mosi_hs: spi2-mosi-hs { 1439 rockchip,pins = 1440 <1 RK_PC7 3 &pcfg_pull_up_8ma>; 1441 }; 1442 }; 1443 1444 sdmmc { 1445 sdmmc_clk: sdmmc-clk { 1446 rockchip,pins = 1447 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1448 }; 1449 1450 sdmmc_cmd: sdmmc-cmd { 1451 rockchip,pins = 1452 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1453 }; 1454 1455 sdmmc_det: sdmmc-det { 1456 rockchip,pins = 1457 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1458 }; 1459 1460 sdmmc_pwren: sdmmc-pwren { 1461 rockchip,pins = 1462 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1463 }; 1464 1465 sdmmc_bus1: sdmmc-bus1 { 1466 rockchip,pins = 1467 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1468 }; 1469 1470 sdmmc_bus4: sdmmc-bus4 { 1471 rockchip,pins = 1472 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1473 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1474 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1475 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1476 }; 1477 1478 sdmmc_gpio: sdmmc-gpio { 1479 rockchip,pins = 1480 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 1481 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 1482 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 1483 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 1484 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 1485 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 1486 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 1487 }; 1488 }; 1489 1490 sdio { 1491 sdio_clk: sdio-clk { 1492 rockchip,pins = 1493 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1494 }; 1495 1496 sdio_cmd: sdio-cmd { 1497 rockchip,pins = 1498 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1499 }; 1500 1501 sdio_pwren: sdio-pwren { 1502 rockchip,pins = 1503 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1504 }; 1505 1506 sdio_wrpt: sdio-wrpt { 1507 rockchip,pins = 1508 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1509 }; 1510 1511 sdio_intn: sdio-intn { 1512 rockchip,pins = 1513 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1514 }; 1515 1516 sdio_bus1: sdio-bus1 { 1517 rockchip,pins = 1518 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1519 }; 1520 1521 sdio_bus4: sdio-bus4 { 1522 rockchip,pins = 1523 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1524 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1525 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1526 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1527 }; 1528 1529 sdio_gpio: sdio-gpio { 1530 rockchip,pins = 1531 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 1532 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 1533 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 1534 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 1535 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 1536 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 1537 }; 1538 }; 1539 1540 emmc { 1541 emmc_clk: emmc-clk { 1542 rockchip,pins = 1543 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 1544 }; 1545 1546 emmc_cmd: emmc-cmd { 1547 rockchip,pins = 1548 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 1549 }; 1550 1551 emmc_pwren: emmc-pwren { 1552 rockchip,pins = 1553 <3 RK_PB3 2 &pcfg_pull_none>; 1554 }; 1555 1556 emmc_rstn: emmc-rstn { 1557 rockchip,pins = 1558 <3 RK_PB2 2 &pcfg_pull_none>; 1559 }; 1560 1561 emmc_bus1: emmc-bus1 { 1562 rockchip,pins = 1563 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 1564 }; 1565 1566 emmc_bus4: emmc-bus4 { 1567 rockchip,pins = 1568 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1569 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1570 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1571 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 1572 }; 1573 1574 emmc_bus8: emmc-bus8 { 1575 rockchip,pins = 1576 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 1577 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 1578 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 1579 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 1580 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 1581 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 1582 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 1583 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 1584 }; 1585 }; 1586 1587 flash { 1588 flash_csn0: flash-csn0 { 1589 rockchip,pins = 1590 <3 RK_PB5 1 &pcfg_pull_none>; 1591 }; 1592 1593 flash_rdy: flash-rdy { 1594 rockchip,pins = 1595 <3 RK_PB4 1 &pcfg_pull_none>; 1596 }; 1597 1598 flash_ale: flash-ale { 1599 rockchip,pins = 1600 <3 RK_PB3 1 &pcfg_pull_none>; 1601 }; 1602 1603 flash_cle: flash-cle { 1604 rockchip,pins = 1605 <3 RK_PB1 1 &pcfg_pull_none>; 1606 }; 1607 1608 flash_wrn: flash-wrn { 1609 rockchip,pins = 1610 <3 RK_PB0 1 &pcfg_pull_none>; 1611 }; 1612 1613 flash_rdn: flash-rdn { 1614 rockchip,pins = 1615 <3 RK_PB2 1 &pcfg_pull_none>; 1616 }; 1617 1618 flash_bus8: flash-bus8 { 1619 rockchip,pins = 1620 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1621 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1622 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1623 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1624 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1625 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1626 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1627 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1628 }; 1629 }; 1630 1631 pwm0 { 1632 pwm0_pin: pwm0-pin { 1633 rockchip,pins = 1634 <0 RK_PB5 1 &pcfg_pull_none>; 1635 }; 1636 1637 pwm0_pin_pull_down: pwm0-pin-pull-down { 1638 rockchip,pins = 1639 <0 RK_PB5 1 &pcfg_pull_down>; 1640 }; 1641 }; 1642 1643 pwm1 { 1644 pwm1_pin: pwm1-pin { 1645 rockchip,pins = 1646 <0 RK_PB6 1 &pcfg_pull_none>; 1647 }; 1648 1649 pwm1_pin_pull_down: pwm1-pin-pull-down { 1650 rockchip,pins = 1651 <0 RK_PB6 1 &pcfg_pull_down>; 1652 }; 1653 }; 1654 1655 pwm2 { 1656 pwm2_pin: pwm2-pin { 1657 rockchip,pins = 1658 <0 RK_PB7 1 &pcfg_pull_none>; 1659 }; 1660 1661 pwm2_pin_pull_down: pwm2-pin-pull-down { 1662 rockchip,pins = 1663 <0 RK_PB7 1 &pcfg_pull_down>; 1664 }; 1665 }; 1666 1667 pwm3 { 1668 pwm3_pin: pwm3-pin { 1669 rockchip,pins = 1670 <0 RK_PC0 1 &pcfg_pull_none>; 1671 }; 1672 1673 pwm3_pin_pull_down: pwm3-pin-pull-down { 1674 rockchip,pins = 1675 <0 RK_PC0 1 &pcfg_pull_down>; 1676 }; 1677 }; 1678 1679 pwm4 { 1680 pwm4_pin: pwm4-pin { 1681 rockchip,pins = 1682 <0 RK_PA1 2 &pcfg_pull_none>; 1683 }; 1684 1685 pwm4_pin_pull_down: pwm4-pin-pull-down { 1686 rockchip,pins = 1687 <0 RK_PA1 2 &pcfg_pull_down>; 1688 }; 1689 }; 1690 1691 pwm5 { 1692 pwm5_pin: pwm5-pin { 1693 rockchip,pins = 1694 <0 RK_PC1 2 &pcfg_pull_none>; 1695 }; 1696 1697 pwm5_pin_pull_down: pwm5-pin-pull-down { 1698 rockchip,pins = 1699 <0 RK_PC1 2 &pcfg_pull_down>; 1700 }; 1701 }; 1702 1703 pwm6 { 1704 pwm6_pin: pwm6-pin { 1705 rockchip,pins = 1706 <0 RK_PC2 2 &pcfg_pull_none>; 1707 }; 1708 1709 pwm6_pin_pull_down: pwm6-pin-pull-down { 1710 rockchip,pins = 1711 <0 RK_PC2 2 &pcfg_pull_down>; 1712 }; 1713 }; 1714 1715 pwm7 { 1716 pwm7_pin: pwm7-pin { 1717 rockchip,pins = 1718 <2 RK_PB0 2 &pcfg_pull_none>; 1719 }; 1720 1721 pwm7_pin_pull_down: pwm7-pin-pull-down { 1722 rockchip,pins = 1723 <2 RK_PB0 2 &pcfg_pull_down>; 1724 }; 1725 }; 1726 1727 pwm8 { 1728 pwm8_pin: pwm8-pin { 1729 rockchip,pins = 1730 <2 RK_PB2 2 &pcfg_pull_none>; 1731 }; 1732 1733 pwm8_pin_pull_down: pwm8-pin-pull-down { 1734 rockchip,pins = 1735 <2 RK_PB2 2 &pcfg_pull_down>; 1736 }; 1737 }; 1738 1739 pwm9 { 1740 pwm9_pin: pwm9-pin { 1741 rockchip,pins = 1742 <2 RK_PB3 2 &pcfg_pull_none>; 1743 }; 1744 1745 pwm9_pin_pull_down: pwm9-pin-pull-down { 1746 rockchip,pins = 1747 <2 RK_PB3 2 &pcfg_pull_down>; 1748 }; 1749 }; 1750 1751 pwm10 { 1752 pwm10_pin: pwm10-pin { 1753 rockchip,pins = 1754 <2 RK_PB4 2 &pcfg_pull_none>; 1755 }; 1756 1757 pwm10_pin_pull_down: pwm10-pin-pull-down { 1758 rockchip,pins = 1759 <2 RK_PB4 2 &pcfg_pull_down>; 1760 }; 1761 }; 1762 1763 pwm11 { 1764 pwm11_pin: pwm11-pin { 1765 rockchip,pins = 1766 <2 RK_PC0 4 &pcfg_pull_none>; 1767 }; 1768 1769 pwm11_pin_pull_down: pwm11-pin-pull-down { 1770 rockchip,pins = 1771 <2 RK_PC0 4 &pcfg_pull_down>; 1772 }; 1773 }; 1774 1775 gmac { 1776 rmii_pins: rmii-pins { 1777 rockchip,pins = 1778 /* mac_txen */ 1779 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1780 /* mac_txd1 */ 1781 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1782 /* mac_txd0 */ 1783 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1784 /* mac_rxd0 */ 1785 <1 RK_PC4 3 &pcfg_pull_none>, 1786 /* mac_rxd1 */ 1787 <1 RK_PC5 3 &pcfg_pull_none>, 1788 /* mac_rxer */ 1789 <1 RK_PB7 3 &pcfg_pull_none>, 1790 /* mac_rxdv */ 1791 <1 RK_PC0 3 &pcfg_pull_none>, 1792 /* mac_mdio */ 1793 <1 RK_PB6 3 &pcfg_pull_none>, 1794 /* mac_mdc */ 1795 <1 RK_PB5 3 &pcfg_pull_none>; 1796 }; 1797 1798 mac_refclk_12ma: mac-refclk-12ma { 1799 rockchip,pins = 1800 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1801 }; 1802 1803 mac_refclk: mac-refclk { 1804 rockchip,pins = 1805 <1 RK_PB4 3 &pcfg_pull_none>; 1806 }; 1807 }; 1808 1809 gmac-m1 { 1810 rmiim1_pins: rmiim1-pins { 1811 rockchip,pins = 1812 /* mac_txen */ 1813 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 1814 /* mac_txd1 */ 1815 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 1816 /* mac_txd0 */ 1817 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 1818 /* mac_rxd0 */ 1819 <4 RK_PA2 2 &pcfg_pull_none>, 1820 /* mac_rxd1 */ 1821 <4 RK_PA3 2 &pcfg_pull_none>, 1822 /* mac_rxer */ 1823 <4 RK_PA0 2 &pcfg_pull_none>, 1824 /* mac_rxdv */ 1825 <4 RK_PA1 2 &pcfg_pull_none>, 1826 /* mac_mdio */ 1827 <4 RK_PB6 2 &pcfg_pull_none>, 1828 /* mac_mdc */ 1829 <4 RK_PB5 2 &pcfg_pull_none>; 1830 }; 1831 1832 macm1_refclk_12ma: macm1-refclk-12ma { 1833 rockchip,pins = 1834 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 1835 }; 1836 1837 macm1_refclk: macm1-refclk { 1838 rockchip,pins = 1839 <4 RK_PB4 2 &pcfg_pull_none>; 1840 }; 1841 }; 1842 1843 rtc { 1844 rtc_32k: rtc-32k { 1845 rockchip,pins = 1846 <0 RK_PC3 1 &pcfg_pull_none>; 1847 }; 1848 }; 1849 1850 }; 1851}; 1852