1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 adc1_in6_pins_a: adc1-in6-0 { 10 pins { 11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>; 12 }; 13 }; 14 15 adc12_ain_pins_a: adc12-ain-0 { 16 pins { 17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ 18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ 20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ 21 }; 22 }; 23 24 adc12_ain_pins_b: adc12-ain-1 { 25 pins { 26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ 28 }; 29 }; 30 31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { 32 pins { 33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ 34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ 35 }; 36 }; 37 38 cec_pins_a: cec-0 { 39 pins { 40 pinmux = <STM32_PINMUX('A', 15, AF4)>; 41 bias-disable; 42 drive-open-drain; 43 slew-rate = <0>; 44 }; 45 }; 46 47 cec_sleep_pins_a: cec-sleep-0 { 48 pins { 49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ 50 }; 51 }; 52 53 cec_pins_b: cec-1 { 54 pins { 55 pinmux = <STM32_PINMUX('B', 6, AF5)>; 56 bias-disable; 57 drive-open-drain; 58 slew-rate = <0>; 59 }; 60 }; 61 62 cec_sleep_pins_b: cec-sleep-1 { 63 pins { 64 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ 65 }; 66 }; 67 68 dac_ch1_pins_a: dac-ch1-0 { 69 pins { 70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; 71 }; 72 }; 73 74 dac_ch2_pins_a: dac-ch2-0 { 75 pins { 76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>; 77 }; 78 }; 79 80 dcmi_pins_a: dcmi-0 { 81 pins { 82 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 83 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ 86 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 87 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 88 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ 89 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 91 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 92 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 94 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ 95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ 96 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ 97 bias-disable; 98 }; 99 }; 100 101 dcmi_sleep_pins_a: dcmi-sleep-0 { 102 pins { 103 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 104 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ 107 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 108 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 109 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ 110 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 112 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 113 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 115 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ 116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ 117 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ 118 }; 119 }; 120 121 ethernet0_rgmii_pins_a: rgmii-0 { 122 pins1 { 123 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 124 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 125 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 126 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 127 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 128 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 129 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 130 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 131 bias-disable; 132 drive-push-pull; 133 slew-rate = <2>; 134 }; 135 pins2 { 136 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 137 bias-disable; 138 drive-push-pull; 139 slew-rate = <0>; 140 }; 141 pins3 { 142 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 143 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 144 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 145 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 146 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 147 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 148 bias-disable; 149 }; 150 }; 151 152 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { 153 pins1 { 154 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 155 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 156 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 157 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 158 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 159 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 160 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 161 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 162 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 163 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 164 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 165 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ 166 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 167 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 168 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 169 }; 170 }; 171 172 ethernet0_rgmii_pins_b: rgmii-1 { 173 pins1 { 174 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 175 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 176 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 177 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 178 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 179 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 180 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 181 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 182 bias-disable; 183 drive-push-pull; 184 slew-rate = <2>; 185 }; 186 pins2 { 187 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 188 bias-disable; 189 drive-push-pull; 190 slew-rate = <0>; 191 }; 192 pins3 { 193 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 194 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 195 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 196 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ 197 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 198 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 199 bias-disable; 200 }; 201 }; 202 203 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { 204 pins1 { 205 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 206 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 207 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 208 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 209 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 210 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 211 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 212 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 213 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 214 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 215 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 216 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 217 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ 218 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 219 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 220 }; 221 }; 222 223 ethernet0_rgmii_pins_c: rgmii-2 { 224 pins1 { 225 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 226 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 227 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ 228 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 229 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 230 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 231 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 232 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 233 bias-disable; 234 drive-push-pull; 235 slew-rate = <2>; 236 }; 237 pins2 { 238 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 239 bias-disable; 240 drive-push-pull; 241 slew-rate = <0>; 242 }; 243 pins3 { 244 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 245 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 246 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 247 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 248 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 249 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 250 bias-disable; 251 }; 252 }; 253 254 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { 255 pins1 { 256 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 257 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 258 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ 259 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 260 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 261 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 262 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 263 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 264 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 265 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 266 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 267 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 268 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 269 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 270 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 271 }; 272 }; 273 274 ethernet0_rmii_pins_a: rmii-0 { 275 pins1 { 276 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 277 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 278 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 279 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ 280 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 281 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 282 bias-disable; 283 drive-push-pull; 284 slew-rate = <2>; 285 }; 286 pins2 { 287 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 288 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 289 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 290 bias-disable; 291 }; 292 }; 293 294 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { 295 pins1 { 296 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 297 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 298 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 299 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 300 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 301 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 302 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 303 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 304 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 305 }; 306 }; 307 308 fmc_pins_a: fmc-0 { 309 pins1 { 310 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 311 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 312 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 313 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 314 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 315 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 316 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 317 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 318 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 319 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 320 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 321 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 322 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 323 bias-disable; 324 drive-push-pull; 325 slew-rate = <1>; 326 }; 327 pins2 { 328 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 329 bias-pull-up; 330 }; 331 }; 332 333 fmc_sleep_pins_a: fmc-sleep-0 { 334 pins { 335 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 336 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 337 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ 338 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ 339 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 340 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 341 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 342 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 343 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 344 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 345 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 346 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 347 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ 348 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ 349 }; 350 }; 351 352 fmc_pins_b: fmc-1 { 353 pins { 354 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 355 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 356 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ 357 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 358 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 359 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 360 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 361 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 362 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 363 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 364 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 365 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ 366 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ 367 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ 368 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ 369 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ 370 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ 371 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ 372 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ 373 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ 374 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ 375 bias-disable; 376 drive-push-pull; 377 slew-rate = <3>; 378 }; 379 }; 380 381 fmc_sleep_pins_b: fmc-sleep-1 { 382 pins { 383 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 384 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 385 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ 386 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 387 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 388 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 389 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 390 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 391 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 392 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 393 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 394 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ 395 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ 396 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ 397 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ 398 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ 399 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ 400 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ 401 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ 402 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ 403 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ 404 }; 405 }; 406 407 i2c1_pins_a: i2c1-0 { 408 pins { 409 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 410 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 411 bias-disable; 412 drive-open-drain; 413 slew-rate = <0>; 414 }; 415 }; 416 417 i2c1_sleep_pins_a: i2c1-sleep-0 { 418 pins { 419 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 420 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 421 }; 422 }; 423 424 i2c1_pins_b: i2c1-1 { 425 pins { 426 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ 427 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 428 bias-disable; 429 drive-open-drain; 430 slew-rate = <0>; 431 }; 432 }; 433 434 i2c1_sleep_pins_b: i2c1-sleep-1 { 435 pins { 436 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ 437 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 438 }; 439 }; 440 441 i2c2_pins_a: i2c2-0 { 442 pins { 443 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 444 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 445 bias-disable; 446 drive-open-drain; 447 slew-rate = <0>; 448 }; 449 }; 450 451 i2c2_sleep_pins_a: i2c2-sleep-0 { 452 pins { 453 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ 454 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 455 }; 456 }; 457 458 i2c2_pins_b1: i2c2-1 { 459 pins { 460 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 461 bias-disable; 462 drive-open-drain; 463 slew-rate = <0>; 464 }; 465 }; 466 467 i2c2_sleep_pins_b1: i2c2-sleep-1 { 468 pins { 469 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 470 }; 471 }; 472 473 i2c2_pins_c: i2c2-2 { 474 pins { 475 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ 476 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 477 bias-disable; 478 drive-open-drain; 479 slew-rate = <0>; 480 }; 481 }; 482 483 i2c2_pins_sleep_c: i2c2-sleep-2 { 484 pins { 485 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ 486 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 487 }; 488 }; 489 490 i2c5_pins_a: i2c5-0 { 491 pins { 492 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ 493 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ 494 bias-disable; 495 drive-open-drain; 496 slew-rate = <0>; 497 }; 498 }; 499 500 i2c5_sleep_pins_a: i2c5-sleep-0 { 501 pins { 502 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ 503 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ 504 505 }; 506 }; 507 508 i2c5_pins_b: i2c5-1 { 509 pins { 510 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ 511 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ 512 bias-disable; 513 drive-open-drain; 514 slew-rate = <0>; 515 }; 516 }; 517 518 i2c5_sleep_pins_b: i2c5-sleep-1 { 519 pins { 520 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ 521 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ 522 }; 523 }; 524 525 i2s2_pins_a: i2s2-0 { 526 pins { 527 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ 528 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ 529 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ 530 slew-rate = <1>; 531 drive-push-pull; 532 bias-disable; 533 }; 534 }; 535 536 i2s2_sleep_pins_a: i2s2-sleep-0 { 537 pins { 538 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ 539 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ 540 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ 541 }; 542 }; 543 544 ltdc_pins_a: ltdc-0 { 545 pins { 546 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ 547 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 548 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 549 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ 550 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ 551 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 552 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 553 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 554 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ 555 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ 556 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 557 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 558 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 559 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ 560 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 561 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ 562 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 563 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ 564 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ 565 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ 566 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 567 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 568 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 569 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 570 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ 571 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 572 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 573 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ 574 bias-disable; 575 drive-push-pull; 576 slew-rate = <1>; 577 }; 578 }; 579 580 ltdc_sleep_pins_a: ltdc-sleep-0 { 581 pins { 582 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 583 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 584 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 585 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ 586 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ 587 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 588 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 589 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 590 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ 591 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ 592 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 593 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 594 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 595 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ 596 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 597 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ 598 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 599 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ 600 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ 601 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ 602 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 603 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 604 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 605 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 606 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ 607 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 608 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 609 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ 610 }; 611 }; 612 613 ltdc_pins_b: ltdc-1 { 614 pins { 615 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 616 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 617 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 618 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ 619 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 620 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 621 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 622 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 623 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 624 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 625 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ 626 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 627 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 628 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 629 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 630 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 631 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 632 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 633 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 634 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 635 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 636 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 637 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 638 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ 639 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 640 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 641 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 642 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ 643 bias-disable; 644 drive-push-pull; 645 slew-rate = <1>; 646 }; 647 }; 648 649 ltdc_sleep_pins_b: ltdc-sleep-1 { 650 pins { 651 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ 652 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ 653 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ 654 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ 655 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ 656 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ 657 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ 658 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ 659 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ 660 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ 661 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ 662 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ 663 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ 664 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ 665 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ 666 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ 667 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ 668 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ 669 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ 670 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ 671 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ 672 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ 673 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ 674 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ 675 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ 676 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ 677 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ 678 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ 679 }; 680 }; 681 682 ltdc_pins_c: ltdc-2 { 683 pins1 { 684 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ 685 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ 686 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ 687 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ 688 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ 689 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ 690 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ 691 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ 692 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ 693 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ 694 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ 695 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ 696 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ 697 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ 698 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ 699 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ 700 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ 701 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ 702 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ 703 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ 704 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ 705 bias-disable; 706 drive-push-pull; 707 slew-rate = <0>; 708 }; 709 pins2 { 710 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ 711 bias-disable; 712 drive-push-pull; 713 slew-rate = <1>; 714 }; 715 }; 716 717 ltdc_sleep_pins_c: ltdc-sleep-2 { 718 pins1 { 719 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ 720 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ 721 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ 722 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ 723 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ 724 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ 725 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ 726 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ 727 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ 728 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ 729 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ 730 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ 731 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ 732 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ 733 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ 734 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ 735 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ 736 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ 737 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ 738 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ 739 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ 740 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ 741 }; 742 }; 743 744 ltdc_pins_d: ltdc-3 { 745 pins1 { 746 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ 747 bias-disable; 748 drive-push-pull; 749 slew-rate = <3>; 750 }; 751 pins2 { 752 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 753 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 754 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ 755 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ 756 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 757 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 758 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 759 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ 760 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ 761 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 762 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 763 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 764 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ 765 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 766 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ 767 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 768 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ 769 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ 770 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ 771 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 772 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 773 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 774 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 775 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ 776 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 777 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 778 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ 779 bias-disable; 780 drive-push-pull; 781 slew-rate = <2>; 782 }; 783 }; 784 785 ltdc_sleep_pins_d: ltdc-sleep-3 { 786 pins { 787 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 788 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 789 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 790 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ 791 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ 792 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 793 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 794 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 795 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ 796 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ 797 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 798 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 799 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 800 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ 801 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 802 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ 803 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 804 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ 805 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ 806 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ 807 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 808 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 809 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 810 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 811 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ 812 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 813 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 814 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ 815 }; 816 }; 817 818 m_can1_pins_a: m-can1-0 { 819 pins1 { 820 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 821 slew-rate = <1>; 822 drive-push-pull; 823 bias-disable; 824 }; 825 pins2 { 826 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ 827 bias-disable; 828 }; 829 }; 830 831 m_can1_sleep_pins_a: m_can1-sleep-0 { 832 pins { 833 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 834 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ 835 }; 836 }; 837 838 m_can1_pins_b: m-can1-1 { 839 pins1 { 840 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ 841 slew-rate = <1>; 842 drive-push-pull; 843 bias-disable; 844 }; 845 pins2 { 846 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ 847 bias-disable; 848 }; 849 }; 850 851 m_can1_sleep_pins_b: m_can1-sleep-1 { 852 pins { 853 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ 854 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ 855 }; 856 }; 857 858 m_can2_pins_a: m-can2-0 { 859 pins1 { 860 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 861 slew-rate = <1>; 862 drive-push-pull; 863 bias-disable; 864 }; 865 pins2 { 866 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 867 bias-disable; 868 }; 869 }; 870 871 m_can2_sleep_pins_a: m_can2-sleep-0 { 872 pins { 873 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ 874 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ 875 }; 876 }; 877 878 pwm1_pins_a: pwm1-0 { 879 pins { 880 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ 881 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ 882 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ 883 bias-pull-down; 884 drive-push-pull; 885 slew-rate = <0>; 886 }; 887 }; 888 889 pwm1_sleep_pins_a: pwm1-sleep-0 { 890 pins { 891 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ 892 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ 893 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ 894 }; 895 }; 896 897 pwm2_pins_a: pwm2-0 { 898 pins { 899 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ 900 bias-pull-down; 901 drive-push-pull; 902 slew-rate = <0>; 903 }; 904 }; 905 906 pwm2_sleep_pins_a: pwm2-sleep-0 { 907 pins { 908 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ 909 }; 910 }; 911 912 pwm3_pins_a: pwm3-0 { 913 pins { 914 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ 915 bias-pull-down; 916 drive-push-pull; 917 slew-rate = <0>; 918 }; 919 }; 920 921 pwm3_sleep_pins_a: pwm3-sleep-0 { 922 pins { 923 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ 924 }; 925 }; 926 927 pwm3_pins_b: pwm3-1 { 928 pins { 929 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 930 bias-disable; 931 drive-push-pull; 932 slew-rate = <0>; 933 }; 934 }; 935 936 pwm3_sleep_pins_b: pwm3-sleep-1 { 937 pins { 938 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ 939 }; 940 }; 941 942 pwm4_pins_a: pwm4-0 { 943 pins { 944 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ 945 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ 946 bias-pull-down; 947 drive-push-pull; 948 slew-rate = <0>; 949 }; 950 }; 951 952 pwm4_sleep_pins_a: pwm4-sleep-0 { 953 pins { 954 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ 955 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ 956 }; 957 }; 958 959 pwm4_pins_b: pwm4-1 { 960 pins { 961 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 962 bias-pull-down; 963 drive-push-pull; 964 slew-rate = <0>; 965 }; 966 }; 967 968 pwm4_sleep_pins_b: pwm4-sleep-1 { 969 pins { 970 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 971 }; 972 }; 973 974 pwm5_pins_a: pwm5-0 { 975 pins { 976 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ 977 bias-pull-down; 978 drive-push-pull; 979 slew-rate = <0>; 980 }; 981 }; 982 983 pwm5_sleep_pins_a: pwm5-sleep-0 { 984 pins { 985 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ 986 }; 987 }; 988 989 pwm5_pins_b: pwm5-1 { 990 pins { 991 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ 992 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ 993 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ 994 bias-disable; 995 drive-push-pull; 996 slew-rate = <0>; 997 }; 998 }; 999 1000 pwm5_sleep_pins_b: pwm5-sleep-1 { 1001 pins { 1002 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ 1003 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ 1004 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ 1005 }; 1006 }; 1007 1008 pwm8_pins_a: pwm8-0 { 1009 pins { 1010 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ 1011 bias-pull-down; 1012 drive-push-pull; 1013 slew-rate = <0>; 1014 }; 1015 }; 1016 1017 pwm8_sleep_pins_a: pwm8-sleep-0 { 1018 pins { 1019 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ 1020 }; 1021 }; 1022 1023 pwm12_pins_a: pwm12-0 { 1024 pins { 1025 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ 1026 bias-pull-down; 1027 drive-push-pull; 1028 slew-rate = <0>; 1029 }; 1030 }; 1031 1032 pwm12_sleep_pins_a: pwm12-sleep-0 { 1033 pins { 1034 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ 1035 }; 1036 }; 1037 1038 qspi_clk_pins_a: qspi-clk-0 { 1039 pins { 1040 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 1041 bias-disable; 1042 drive-push-pull; 1043 slew-rate = <3>; 1044 }; 1045 }; 1046 1047 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 1048 pins { 1049 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 1050 }; 1051 }; 1052 1053 qspi_bk1_pins_a: qspi-bk1-0 { 1054 pins1 { 1055 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 1056 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 1057 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 1058 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 1059 bias-disable; 1060 drive-push-pull; 1061 slew-rate = <1>; 1062 }; 1063 pins2 { 1064 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 1065 bias-pull-up; 1066 drive-push-pull; 1067 slew-rate = <1>; 1068 }; 1069 }; 1070 1071 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 1072 pins { 1073 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 1074 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 1075 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ 1076 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ 1077 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ 1078 }; 1079 }; 1080 1081 qspi_bk2_pins_a: qspi-bk2-0 { 1082 pins1 { 1083 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 1084 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 1085 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 1086 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 1087 bias-disable; 1088 drive-push-pull; 1089 slew-rate = <1>; 1090 }; 1091 pins2 { 1092 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 1093 bias-pull-up; 1094 drive-push-pull; 1095 slew-rate = <1>; 1096 }; 1097 }; 1098 1099 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { 1100 pins { 1101 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ 1102 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ 1103 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ 1104 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ 1105 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ 1106 }; 1107 }; 1108 1109 sai2a_pins_a: sai2a-0 { 1110 pins { 1111 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ 1112 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1113 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1114 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ 1115 slew-rate = <0>; 1116 drive-push-pull; 1117 bias-disable; 1118 }; 1119 }; 1120 1121 sai2a_sleep_pins_a: sai2a-sleep-0 { 1122 pins { 1123 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ 1124 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1125 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1126 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ 1127 }; 1128 }; 1129 1130 sai2a_pins_b: sai2a-1 { 1131 pins1 { 1132 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1133 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1134 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ 1135 slew-rate = <0>; 1136 drive-push-pull; 1137 bias-disable; 1138 }; 1139 }; 1140 1141 sai2a_sleep_pins_b: sai2a-sleep-1 { 1142 pins { 1143 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1144 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1145 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ 1146 }; 1147 }; 1148 1149 sai2a_pins_c: sai2a-4 { 1150 pins { 1151 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ 1152 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ 1153 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ 1154 slew-rate = <0>; 1155 drive-push-pull; 1156 bias-disable; 1157 }; 1158 }; 1159 1160 sai2a_sleep_pins_c: sai2a-5 { 1161 pins { 1162 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ 1163 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ 1164 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ 1165 }; 1166 }; 1167 1168 sai2b_pins_a: sai2b-0 { 1169 pins1 { 1170 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ 1171 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ 1172 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ 1173 slew-rate = <0>; 1174 drive-push-pull; 1175 bias-disable; 1176 }; 1177 pins2 { 1178 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1179 bias-disable; 1180 }; 1181 }; 1182 1183 sai2b_sleep_pins_a: sai2b-sleep-0 { 1184 pins { 1185 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ 1186 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ 1187 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ 1188 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ 1189 }; 1190 }; 1191 1192 sai2b_pins_b: sai2b-1 { 1193 pins { 1194 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1195 bias-disable; 1196 }; 1197 }; 1198 1199 sai2b_sleep_pins_b: sai2b-sleep-1 { 1200 pins { 1201 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1202 }; 1203 }; 1204 1205 sai2b_pins_c: sai2a-4 { 1206 pins1 { 1207 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1208 bias-disable; 1209 }; 1210 }; 1211 1212 sai2b_sleep_pins_c: sai2a-sleep-5 { 1213 pins { 1214 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1215 }; 1216 }; 1217 1218 sai4a_pins_a: sai4a-0 { 1219 pins { 1220 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ 1221 slew-rate = <0>; 1222 drive-push-pull; 1223 bias-disable; 1224 }; 1225 }; 1226 1227 sai4a_sleep_pins_a: sai4a-sleep-0 { 1228 pins { 1229 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ 1230 }; 1231 }; 1232 1233 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 1234 pins1 { 1235 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1236 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1237 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1238 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 1239 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1240 slew-rate = <1>; 1241 drive-push-pull; 1242 bias-disable; 1243 }; 1244 pins2 { 1245 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1246 slew-rate = <2>; 1247 drive-push-pull; 1248 bias-disable; 1249 }; 1250 }; 1251 1252 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 1253 pins1 { 1254 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1255 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1256 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1257 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1258 slew-rate = <1>; 1259 drive-push-pull; 1260 bias-disable; 1261 }; 1262 pins2 { 1263 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1264 slew-rate = <2>; 1265 drive-push-pull; 1266 bias-disable; 1267 }; 1268 pins3 { 1269 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1270 slew-rate = <1>; 1271 drive-open-drain; 1272 bias-disable; 1273 }; 1274 }; 1275 1276 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 1277 pins { 1278 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 1279 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 1280 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 1281 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 1282 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 1283 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 1284 }; 1285 }; 1286 1287 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 1288 pins1 { 1289 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1290 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1291 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1292 slew-rate = <1>; 1293 drive-push-pull; 1294 bias-pull-up; 1295 }; 1296 pins2{ 1297 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1298 bias-pull-up; 1299 }; 1300 }; 1301 1302 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 1303 pins { 1304 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1305 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 1306 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1307 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1308 }; 1309 }; 1310 1311 sdmmc1_dir_pins_b: sdmmc1-dir-1 { 1312 pins1 { 1313 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1314 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ 1315 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1316 slew-rate = <1>; 1317 drive-push-pull; 1318 bias-pull-up; 1319 }; 1320 pins2{ 1321 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1322 bias-pull-up; 1323 }; 1324 }; 1325 1326 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { 1327 pins { 1328 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1329 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ 1330 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1331 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1332 }; 1333 }; 1334 1335 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 1336 pins1 { 1337 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1338 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1339 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1340 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1341 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1342 slew-rate = <1>; 1343 drive-push-pull; 1344 bias-pull-up; 1345 }; 1346 pins2 { 1347 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1348 slew-rate = <2>; 1349 drive-push-pull; 1350 bias-pull-up; 1351 }; 1352 }; 1353 1354 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 1355 pins1 { 1356 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1357 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1358 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1359 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1360 slew-rate = <1>; 1361 drive-push-pull; 1362 bias-pull-up; 1363 }; 1364 pins2 { 1365 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1366 slew-rate = <2>; 1367 drive-push-pull; 1368 bias-pull-up; 1369 }; 1370 pins3 { 1371 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1372 slew-rate = <1>; 1373 drive-open-drain; 1374 bias-pull-up; 1375 }; 1376 }; 1377 1378 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 1379 pins { 1380 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 1381 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 1382 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 1383 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 1384 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 1385 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 1386 }; 1387 }; 1388 1389 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 1390 pins1 { 1391 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1392 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1393 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1394 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1395 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1396 slew-rate = <1>; 1397 drive-push-pull; 1398 bias-disable; 1399 }; 1400 pins2 { 1401 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1402 slew-rate = <2>; 1403 drive-push-pull; 1404 bias-disable; 1405 }; 1406 }; 1407 1408 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { 1409 pins1 { 1410 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1411 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1412 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1413 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1414 slew-rate = <1>; 1415 drive-push-pull; 1416 bias-disable; 1417 }; 1418 pins2 { 1419 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1420 slew-rate = <2>; 1421 drive-push-pull; 1422 bias-disable; 1423 }; 1424 pins3 { 1425 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1426 slew-rate = <1>; 1427 drive-open-drain; 1428 bias-disable; 1429 }; 1430 }; 1431 1432 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 1433 pins { 1434 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1435 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1436 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1437 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 1438 slew-rate = <1>; 1439 drive-push-pull; 1440 bias-pull-up; 1441 }; 1442 }; 1443 1444 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 1445 pins { 1446 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1447 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1448 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1449 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 1450 }; 1451 }; 1452 1453 sdmmc2_d47_pins_b: sdmmc2-d47-1 { 1454 pins { 1455 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1456 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1457 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1458 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1459 slew-rate = <1>; 1460 drive-push-pull; 1461 bias-disable; 1462 }; 1463 }; 1464 1465 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { 1466 pins { 1467 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1468 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1469 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1470 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1471 }; 1472 }; 1473 1474 sdmmc2_d47_pins_c: sdmmc2-d47-2 { 1475 pins { 1476 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1477 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ 1478 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1479 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1480 slew-rate = <1>; 1481 drive-push-pull; 1482 bias-pull-up; 1483 }; 1484 }; 1485 1486 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { 1487 pins { 1488 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1489 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ 1490 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1491 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1492 }; 1493 }; 1494 1495 sdmmc2_d47_pins_d: sdmmc2-d47-3 { 1496 pins { 1497 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1498 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1499 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1500 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1501 }; 1502 }; 1503 1504 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { 1505 pins { 1506 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1507 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1508 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1509 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1510 }; 1511 }; 1512 1513 sdmmc3_b4_pins_a: sdmmc3-b4-0 { 1514 pins1 { 1515 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1516 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1517 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1518 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1519 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ 1520 slew-rate = <1>; 1521 drive-push-pull; 1522 bias-pull-up; 1523 }; 1524 pins2 { 1525 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1526 slew-rate = <2>; 1527 drive-push-pull; 1528 bias-pull-up; 1529 }; 1530 }; 1531 1532 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { 1533 pins1 { 1534 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1535 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1536 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1537 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1538 slew-rate = <1>; 1539 drive-push-pull; 1540 bias-pull-up; 1541 }; 1542 pins2 { 1543 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1544 slew-rate = <2>; 1545 drive-push-pull; 1546 bias-pull-up; 1547 }; 1548 pins3 { 1549 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ 1550 slew-rate = <1>; 1551 drive-open-drain; 1552 bias-pull-up; 1553 }; 1554 }; 1555 1556 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { 1557 pins { 1558 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1559 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1560 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ 1561 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1562 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1563 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ 1564 }; 1565 }; 1566 1567 sdmmc3_b4_pins_b: sdmmc3-b4-1 { 1568 pins1 { 1569 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1570 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1571 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1572 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1573 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ 1574 slew-rate = <1>; 1575 drive-push-pull; 1576 bias-pull-up; 1577 }; 1578 pins2 { 1579 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1580 slew-rate = <2>; 1581 drive-push-pull; 1582 bias-pull-up; 1583 }; 1584 }; 1585 1586 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { 1587 pins1 { 1588 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1589 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1590 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1591 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1592 slew-rate = <1>; 1593 drive-push-pull; 1594 bias-pull-up; 1595 }; 1596 pins2 { 1597 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1598 slew-rate = <2>; 1599 drive-push-pull; 1600 bias-pull-up; 1601 }; 1602 pins3 { 1603 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ 1604 slew-rate = <1>; 1605 drive-open-drain; 1606 bias-pull-up; 1607 }; 1608 }; 1609 1610 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { 1611 pins { 1612 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1613 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1614 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ 1615 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1616 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1617 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ 1618 }; 1619 }; 1620 1621 spdifrx_pins_a: spdifrx-0 { 1622 pins { 1623 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ 1624 bias-disable; 1625 }; 1626 }; 1627 1628 spdifrx_sleep_pins_a: spdifrx-sleep-0 { 1629 pins { 1630 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ 1631 }; 1632 }; 1633 1634 spi2_pins_a: spi2-0 { 1635 pins1 { 1636 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ 1637 <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ 1638 bias-disable; 1639 drive-push-pull; 1640 slew-rate = <1>; 1641 }; 1642 1643 pins2 { 1644 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ 1645 bias-disable; 1646 }; 1647 }; 1648 1649 spi4_pins_a: spi4-0 { 1650 pins { 1651 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ 1652 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ 1653 bias-disable; 1654 drive-push-pull; 1655 slew-rate = <1>; 1656 }; 1657 pins2 { 1658 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ 1659 bias-disable; 1660 }; 1661 }; 1662 1663 stusb1600_pins_a: stusb1600-0 { 1664 pins { 1665 pinmux = <STM32_PINMUX('I', 11, ANALOG)>; 1666 bias-pull-up; 1667 }; 1668 }; 1669 1670 uart4_pins_a: uart4-0 { 1671 pins1 { 1672 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1673 bias-disable; 1674 drive-push-pull; 1675 slew-rate = <0>; 1676 }; 1677 pins2 { 1678 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1679 bias-disable; 1680 }; 1681 }; 1682 1683 uart4_idle_pins_a: uart4-idle-0 { 1684 pins1 { 1685 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ 1686 }; 1687 pins2 { 1688 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1689 bias-disable; 1690 }; 1691 }; 1692 1693 uart4_sleep_pins_a: uart4-sleep-0 { 1694 pins { 1695 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ 1696 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 1697 }; 1698 }; 1699 1700 uart4_pins_b: uart4-1 { 1701 pins1 { 1702 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 1703 bias-disable; 1704 drive-push-pull; 1705 slew-rate = <0>; 1706 }; 1707 pins2 { 1708 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1709 bias-disable; 1710 }; 1711 }; 1712 1713 uart4_pins_c: uart4-2 { 1714 pins1 { 1715 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1716 bias-disable; 1717 drive-push-pull; 1718 slew-rate = <0>; 1719 }; 1720 pins2 { 1721 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1722 bias-disable; 1723 }; 1724 }; 1725 1726 uart7_pins_a: uart7-0 { 1727 pins1 { 1728 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 1729 bias-disable; 1730 drive-push-pull; 1731 slew-rate = <0>; 1732 }; 1733 pins2 { 1734 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ 1735 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ 1736 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ 1737 bias-disable; 1738 }; 1739 }; 1740 1741 uart7_pins_b: uart7-1 { 1742 pins1 { 1743 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ 1744 bias-disable; 1745 drive-push-pull; 1746 slew-rate = <0>; 1747 }; 1748 pins2 { 1749 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ 1750 bias-disable; 1751 }; 1752 }; 1753 1754 uart7_pins_c: uart7-2 { 1755 pins1 { 1756 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 1757 bias-disable; 1758 drive-push-pull; 1759 slew-rate = <0>; 1760 }; 1761 pins2 { 1762 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 1763 bias-disable; 1764 }; 1765 }; 1766 1767 uart7_idle_pins_c: uart7-idle-2 { 1768 pins1 { 1769 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ 1770 }; 1771 pins2 { 1772 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 1773 bias-disable; 1774 }; 1775 }; 1776 1777 uart7_sleep_pins_c: uart7-sleep-2 { 1778 pins { 1779 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ 1780 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ 1781 }; 1782 }; 1783 1784 uart8_pins_a: uart8-0 { 1785 pins1 { 1786 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 1787 bias-disable; 1788 drive-push-pull; 1789 slew-rate = <0>; 1790 }; 1791 pins2 { 1792 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ 1793 bias-disable; 1794 }; 1795 }; 1796 1797 uart8_rtscts_pins_a: uart8rtscts-0 { 1798 pins { 1799 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ 1800 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ 1801 bias-disable; 1802 }; 1803 }; 1804 1805 usart2_pins_a: usart2-0 { 1806 pins1 { 1807 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 1808 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 1809 bias-disable; 1810 drive-push-pull; 1811 slew-rate = <0>; 1812 }; 1813 pins2 { 1814 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 1815 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 1816 bias-disable; 1817 }; 1818 }; 1819 1820 usart2_sleep_pins_a: usart2-sleep-0 { 1821 pins { 1822 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 1823 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 1824 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 1825 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 1826 }; 1827 }; 1828 1829 usart2_pins_b: usart2-1 { 1830 pins1 { 1831 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 1832 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 1833 bias-disable; 1834 drive-push-pull; 1835 slew-rate = <0>; 1836 }; 1837 pins2 { 1838 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ 1839 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ 1840 bias-disable; 1841 }; 1842 }; 1843 1844 usart2_sleep_pins_b: usart2-sleep-1 { 1845 pins { 1846 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 1847 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 1848 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ 1849 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 1850 }; 1851 }; 1852 1853 usart2_pins_c: usart2-2 { 1854 pins1 { 1855 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ 1856 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 1857 bias-disable; 1858 drive-push-pull; 1859 slew-rate = <3>; 1860 }; 1861 pins2 { 1862 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 1863 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 1864 bias-disable; 1865 }; 1866 }; 1867 1868 usart2_idle_pins_c: usart2-idle-2 { 1869 pins1 { 1870 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 1871 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 1872 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 1873 }; 1874 pins2 { 1875 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ 1876 bias-disable; 1877 }; 1878 }; 1879 1880 usart2_sleep_pins_c: usart2-sleep-2 { 1881 pins { 1882 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 1883 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 1884 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 1885 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 1886 }; 1887 }; 1888 1889 usart3_pins_a: usart3-0 { 1890 pins1 { 1891 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 1892 bias-disable; 1893 drive-push-pull; 1894 slew-rate = <0>; 1895 }; 1896 pins2 { 1897 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 1898 bias-disable; 1899 }; 1900 }; 1901 1902 usart3_pins_b: usart3-1 { 1903 pins1 { 1904 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 1905 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 1906 bias-disable; 1907 drive-push-pull; 1908 slew-rate = <0>; 1909 }; 1910 pins2 { 1911 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 1912 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ 1913 bias-disable; 1914 }; 1915 }; 1916 1917 usart3_idle_pins_b: usart3-idle-1 { 1918 pins1 { 1919 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 1920 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 1921 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ 1922 }; 1923 pins2 { 1924 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 1925 bias-disable; 1926 }; 1927 }; 1928 1929 usart3_sleep_pins_b: usart3-sleep-1 { 1930 pins { 1931 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 1932 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 1933 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ 1934 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 1935 }; 1936 }; 1937 1938 usart3_pins_c: usart3-2 { 1939 pins1 { 1940 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 1941 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 1942 bias-disable; 1943 drive-push-pull; 1944 slew-rate = <0>; 1945 }; 1946 pins2 { 1947 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 1948 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ 1949 bias-disable; 1950 }; 1951 }; 1952 1953 usart3_idle_pins_c: usart3-idle-2 { 1954 pins1 { 1955 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 1956 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 1957 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ 1958 }; 1959 pins2 { 1960 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 1961 bias-disable; 1962 }; 1963 }; 1964 1965 usart3_sleep_pins_c: usart3-sleep-2 { 1966 pins { 1967 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 1968 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 1969 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ 1970 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 1971 }; 1972 }; 1973 1974 usbotg_hs_pins_a: usbotg-hs-0 { 1975 pins { 1976 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ 1977 }; 1978 }; 1979 1980 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { 1981 pins { 1982 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ 1983 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ 1984 }; 1985 }; 1986}; 1987 1988&pinctrl_z { 1989 i2c2_pins_b2: i2c2-0 { 1990 pins { 1991 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ 1992 bias-disable; 1993 drive-open-drain; 1994 slew-rate = <0>; 1995 }; 1996 }; 1997 1998 i2c2_sleep_pins_b2: i2c2-sleep-0 { 1999 pins { 2000 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ 2001 }; 2002 }; 2003 2004 i2c4_pins_a: i2c4-0 { 2005 pins { 2006 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 2007 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 2008 bias-disable; 2009 drive-open-drain; 2010 slew-rate = <0>; 2011 }; 2012 }; 2013 2014 i2c4_sleep_pins_a: i2c4-sleep-0 { 2015 pins { 2016 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ 2017 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ 2018 }; 2019 }; 2020 2021 spi1_pins_a: spi1-0 { 2022 pins1 { 2023 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ 2024 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ 2025 bias-disable; 2026 drive-push-pull; 2027 slew-rate = <1>; 2028 }; 2029 2030 pins2 { 2031 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ 2032 bias-disable; 2033 }; 2034 }; 2035}; 2036