1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2014
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <log.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/flow.h>
12 #include <asm/arch/pinmux.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/pmc.h>
16 #include <linux/delay.h>
17 #include "../cpu.h"
18
19 /* Tegra114-specific CPU init code */
enable_cpu_power_rail(void)20 static void enable_cpu_power_rail(void)
21 {
22 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
23 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
24 u32 reg;
25
26 debug("%s entry\n", __func__);
27
28 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
29 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
30 pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
31
32 /*
33 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
34 * set it for 25ms (102MHz * .025)
35 */
36 reg = 0x26E8F0;
37 writel(reg, &pmc->pmc_cpupwrgood_timer);
38
39 /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
40 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
41 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
42
43 /*
44 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
45 * to 408 to satisfy the requirement of having at least 16 CPU clock
46 * cycles before clamp removal.
47 */
48
49 clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
50 setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
51 }
52
enable_cpu_clocks(void)53 static void enable_cpu_clocks(void)
54 {
55 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
56 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
57 u32 reg;
58
59 debug("%s entry\n", __func__);
60
61 /* Wait for PLL-X to lock */
62 do {
63 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
64 } while ((reg & (1 << pllinfo->lock_det)) == 0);
65
66 /* Wait until all clocks are stable */
67 udelay(PLL_STABILIZATION_DELAY);
68
69 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
70 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
71
72 /* Always enable the main CPU complex clocks */
73 clock_enable(PERIPH_ID_CPU);
74 clock_enable(PERIPH_ID_CPULP);
75 clock_enable(PERIPH_ID_CPUG);
76 }
77
remove_cpu_resets(void)78 static void remove_cpu_resets(void)
79 {
80 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
81 u32 reg;
82
83 debug("%s entry\n", __func__);
84 /* Take the slow non-CPU partition out of reset */
85 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
86 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
87
88 /* Take the fast non-CPU partition out of reset */
89 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
90 writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
91
92 /* Clear the SW-controlled reset of the slow cluster */
93 reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
94 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
95 writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
96
97 /* Clear the SW-controlled reset of the fast cluster */
98 reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
99 reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
100 reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
101 reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
102 reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
103 writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
104 }
105
106 /**
107 * Tegra114 requires some special clock initialization, including setting up
108 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
109 */
t114_init_clocks(void)110 void t114_init_clocks(void)
111 {
112 struct clk_rst_ctlr *clkrst =
113 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
114 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
115 u32 val;
116
117 debug("%s entry\n", __func__);
118
119 /* Set active CPU cluster to G */
120 clrbits_le32(&flow->cluster_control, 1);
121
122 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
123
124 debug("Setting up PLLX\n");
125 init_pllx();
126
127 val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
128 writel(val, &clkrst->crc_clk_sys_rate);
129
130 /* Enable clocks to required peripherals. TBD - minimize this list */
131 debug("Enabling clocks\n");
132
133 clock_set_enable(PERIPH_ID_CACHE2, 1);
134 clock_set_enable(PERIPH_ID_GPIO, 1);
135 clock_set_enable(PERIPH_ID_TMR, 1);
136 clock_set_enable(PERIPH_ID_RTC, 1);
137 clock_set_enable(PERIPH_ID_CPU, 1);
138 clock_set_enable(PERIPH_ID_EMC, 1);
139 clock_set_enable(PERIPH_ID_I2C5, 1);
140 clock_set_enable(PERIPH_ID_FUSE, 1);
141 clock_set_enable(PERIPH_ID_PMC, 1);
142 clock_set_enable(PERIPH_ID_APBDMA, 1);
143 clock_set_enable(PERIPH_ID_MEM, 1);
144 clock_set_enable(PERIPH_ID_IRAMA, 1);
145 clock_set_enable(PERIPH_ID_IRAMB, 1);
146 clock_set_enable(PERIPH_ID_IRAMC, 1);
147 clock_set_enable(PERIPH_ID_IRAMD, 1);
148 clock_set_enable(PERIPH_ID_CORESIGHT, 1);
149 clock_set_enable(PERIPH_ID_MSELECT, 1);
150 clock_set_enable(PERIPH_ID_EMC1, 1);
151 clock_set_enable(PERIPH_ID_MC1, 1);
152 clock_set_enable(PERIPH_ID_DVFS, 1);
153
154 /*
155 * Set MSELECT clock source as PLLP (00), and ask for a clock
156 * divider that would set the MSELECT clock at 102MHz for a
157 * PLLP base of 408MHz.
158 */
159 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
160 CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
161
162 /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
163 clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
164
165 /* Give clocks time to stabilize */
166 udelay(1000);
167
168 /* Take required peripherals out of reset */
169 debug("Taking periphs out of reset\n");
170 reset_set_enable(PERIPH_ID_CACHE2, 0);
171 reset_set_enable(PERIPH_ID_GPIO, 0);
172 reset_set_enable(PERIPH_ID_TMR, 0);
173 reset_set_enable(PERIPH_ID_COP, 0);
174 reset_set_enable(PERIPH_ID_EMC, 0);
175 reset_set_enable(PERIPH_ID_I2C5, 0);
176 reset_set_enable(PERIPH_ID_FUSE, 0);
177 reset_set_enable(PERIPH_ID_APBDMA, 0);
178 reset_set_enable(PERIPH_ID_MEM, 0);
179 reset_set_enable(PERIPH_ID_CORESIGHT, 0);
180 reset_set_enable(PERIPH_ID_MSELECT, 0);
181 reset_set_enable(PERIPH_ID_EMC1, 0);
182 reset_set_enable(PERIPH_ID_MC1, 0);
183 reset_set_enable(PERIPH_ID_DVFS, 0);
184
185 debug("%s exit\n", __func__);
186 }
187
is_partition_powered(u32 partid)188 static bool is_partition_powered(u32 partid)
189 {
190 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
191 u32 reg;
192
193 /* Get power gate status */
194 reg = readl(&pmc->pmc_pwrgate_status);
195 return !!(reg & (1 << partid));
196 }
197
is_clamp_enabled(u32 partid)198 static bool is_clamp_enabled(u32 partid)
199 {
200 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
201 u32 reg;
202
203 /* Get clamp status. */
204 reg = readl(&pmc->pmc_clamp_status);
205 return !!(reg & (1 << partid));
206 }
207
power_partition(u32 partid)208 static void power_partition(u32 partid)
209 {
210 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
211
212 debug("%s: part ID = %08X\n", __func__, partid);
213 /* Is the partition already on? */
214 if (!is_partition_powered(partid)) {
215 /* No, toggle the partition power state (OFF -> ON) */
216 debug("power_partition, toggling state\n");
217 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
218
219 /* Wait for the power to come up */
220 while (!is_partition_powered(partid))
221 ;
222
223 /* Wait for the clamp status to be cleared */
224 while (is_clamp_enabled(partid))
225 ;
226
227 /* Give I/O signals time to stabilize */
228 udelay(IO_STABILIZATION_DELAY);
229 }
230 }
231
powerup_cpus(void)232 void powerup_cpus(void)
233 {
234 /* We boot to the fast cluster */
235 debug("%s entry: G cluster\n", __func__);
236
237 /* Power up the fast cluster rail partition */
238 power_partition(CRAIL);
239
240 /* Power up the fast cluster non-CPU partition */
241 power_partition(C0NC);
242
243 /* Power up the fast cluster CPU0 partition */
244 power_partition(CE0);
245 }
246
start_cpu(u32 reset_vector)247 void start_cpu(u32 reset_vector)
248 {
249 u32 imme, inst;
250
251 debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
252
253 t114_init_clocks();
254
255 /* Enable VDD_CPU */
256 enable_cpu_power_rail();
257
258 /* Get the CPU(s) running */
259 enable_cpu_clocks();
260
261 /* Enable CoreSight */
262 clock_enable_coresight(1);
263
264 /* Take CPU(s) out of reset */
265 remove_cpu_resets();
266
267 /* Set the entry point for CPU execution from reset */
268
269 /*
270 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
271 * See nvbug 1193357 for details.
272 */
273
274 /* mov r0, #lsb(reset_vector) */
275 imme = reset_vector & 0xffff;
276 inst = imme & 0xfff;
277 inst |= ((imme >> 12) << 16);
278 inst |= 0xe3000000;
279 writel(inst, 0x4003fff0);
280
281 /* movt r0, #msb(reset_vector) */
282 imme = (reset_vector >> 16) & 0xffff;
283 inst = imme & 0xfff;
284 inst |= ((imme >> 12) << 16);
285 inst |= 0xe3400000;
286 writel(inst, 0x4003fff4);
287
288 /* bx r0 */
289 writel(0xe12fff10, 0x4003fff8);
290
291 /* b -12 */
292 imme = (u32)-20;
293 inst = (imme >> 2) & 0xffffff;
294 inst |= 0xea000000;
295 writel(inst, 0x4003fffc);
296
297 /* Write to original location for compatibility */
298 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
299
300 /* If the CPU(s) don't already have power, power 'em up */
301 powerup_cpus();
302 }
303