1/*
2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
3 * Author: Rostislav Lisovy <lisovy@jablotron.cz>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include "am33xx.dtsi"
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	model = "Grinn AM335x ChiliSOM";
14	compatible = "grinn,am335x-chilisom", "ti,am33xx";
15
16	cpus {
17		cpu@0 {
18			cpu0-supply = <&dcdc2_reg>;
19		};
20	};
21
22	memory@80000000 {
23		device_type = "memory";
24		reg = <0x80000000 0x20000000>; /* 512 MB */
25	};
26};
27
28&am33xx_pinmux {
29	pinctrl-names = "default";
30
31	i2c0_pins: pinmux_i2c0_pins {
32		pinctrl-single,pins = <
33			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
34			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
35		>;
36	};
37
38	nandflash_pins: nandflash_pins {
39		pinctrl-single,pins = <
40			AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
41			AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
42			AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
43			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
44			AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
45			AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
46			AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
47			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
48
49			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
50			AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_csn0.gpmc_csn0 */
51			AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_advn_ale.gpmc_advn_ale */
52			AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_oen_ren.gpmc_oen_ren */
53			AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_wen.gpmc_wen */
54			AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_be0n_cle.gpmc_be0n_cle */
55		>;
56	};
57};
58
59&i2c0 {
60	pinctrl-names = "default";
61	pinctrl-0 = <&i2c0_pins>;
62
63	status = "okay";
64	clock-frequency = <400000>;
65
66	tps: tps@24 {
67		reg = <0x24>;
68	};
69
70};
71
72/include/ "tps65217.dtsi"
73
74&tps {
75	regulators {
76		dcdc1_reg: regulator@0 {
77			regulator-name = "vdds_dpr";
78			regulator-always-on;
79		};
80
81		dcdc2_reg: regulator@1 {
82			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
83			regulator-name = "vdd_mpu";
84			regulator-min-microvolt = <925000>;
85			regulator-max-microvolt = <1325000>;
86			regulator-boot-on;
87			regulator-always-on;
88		};
89
90		dcdc3_reg: regulator@2 {
91			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
92			regulator-name = "vdd_core";
93			regulator-min-microvolt = <925000>;
94			regulator-max-microvolt = <1150000>;
95			regulator-boot-on;
96			regulator-always-on;
97		};
98
99		ldo1_reg: regulator@3 {
100			regulator-name = "vio,vrtc,vdds";
101			regulator-boot-on;
102			regulator-always-on;
103		};
104
105		ldo2_reg: regulator@4 {
106			regulator-name = "vdd_3v3aux";
107			regulator-boot-on;
108			regulator-always-on;
109		};
110
111		ldo3_reg: regulator@5 {
112			regulator-name = "vdd_1v8";
113			regulator-boot-on;
114			regulator-always-on;
115		};
116
117		ldo4_reg: regulator@6 {
118			regulator-name = "vdd_3v3d";
119			regulator-boot-on;
120			regulator-always-on;
121		};
122	};
123};
124
125&rtc {
126	system-power-controller;
127
128	pinctrl-0 = <&ext_wakeup>;
129	pinctrl-names = "default";
130
131	ext_wakeup: ext-wakeup {
132		pins = "ext_wakeup0";
133		input-enable;
134	};
135};
136
137/* NAND Flash */
138&elm {
139	status = "okay";
140};
141
142&gpmc {
143	status = "okay";
144	pinctrl-names = "default";
145	pinctrl-0 = <&nandflash_pins>;
146	ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
147	nand@0,0 {
148		compatible = "ti,omap2-nand";
149		reg = <0 0 4>;	/* CS0, offset 0, IO size 4 */
150		interrupt-parent = <&gpmc>;
151		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
152			     <1 IRQ_TYPE_NONE>;	/* termcount */
153		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
154		ti,nand-ecc-opt = "bch8";
155		ti,elm-id = <&elm>;
156		nand-bus-width = <8>;
157		gpmc,device-width = <1>;
158		gpmc,sync-clk-ps = <0>;
159		gpmc,cs-on-ns = <0>;
160		gpmc,cs-rd-off-ns = <44>;
161		gpmc,cs-wr-off-ns = <44>;
162		gpmc,adv-on-ns = <6>;
163		gpmc,adv-rd-off-ns = <34>;
164		gpmc,adv-wr-off-ns = <44>;
165		gpmc,we-on-ns = <0>;
166		gpmc,we-off-ns = <40>;
167		gpmc,oe-on-ns = <0>;
168		gpmc,oe-off-ns = <54>;
169		gpmc,access-ns = <64>;
170		gpmc,rd-cycle-ns = <82>;
171		gpmc,wr-cycle-ns = <82>;
172		gpmc,bus-turnaround-ns = <0>;
173		gpmc,cycle2cycle-delay-ns = <0>;
174		gpmc,clk-activation-ns = <0>;
175		gpmc,wr-access-ns = <40>;
176		gpmc,wr-data-mux-bus-ns = <0>;
177	};
178};
179