1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 - 2021 Marvell International Ltd.
4 */
5
6/*
7 * Device Tree file for Marvell Armada 8040 Development board platform
8 */
9
10#include "armada-8040.dtsi"
11
12/ {
13	model = "Marvell Armada 8040 DB board";
14	compatible = "marvell,armada8040-db", "marvell,armada8040",
15		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
16
17	chosen {
18		stdout-path = "serial0:115200n8";
19	};
20
21	aliases {
22		i2c0 = &cp0_i2c0;
23		spi0 = &cp1_spi1;
24	};
25
26	memory@00000000 {
27		device_type = "memory";
28		reg = <0x0 0x0 0x0 0x80000000>;
29	};
30};
31
32/* Accessible over the mini-USB CON9 connector on the main board */
33&uart0 {
34	status = "okay";
35};
36
37&ap_pinctl {
38	/* MPP Bus:
39	 * SDIO  [0-10]
40	 * UART0 [11,19]
41	 */
42		  /* 0 1 2 3 4 5 6 7 8 9 */
43	pin-func = < 1 1 1 1 1 1 1 1 1 1
44		     1 3 0 0 0 0 0 0 0 3 >;
45};
46
47&ap_sdhci0 {
48	pinctrl-names = "default";
49	pinctrl-0 = <&ap_emmc_pins>;
50	bus-width = <8>;
51	status = "okay";
52};
53
54&cp0_pinctl {
55	/* MPP Bus:
56	 *	[0-31]	= 0xff: Keep default CP0_shared_pins
57	 *	[11]	CLKOUT_MPP_11 (out)
58	 *	[23]	LINK_RD_IN_CP2CP (in)
59	 *	[25]	CLKOUT_MPP_25 (out)
60	 *	[29]	AVS_FB_IN_CP2CP (in)
61	 *	[32,34]	GE_MDIO/MDC
62	 *	[33]	GPIO: GE_INT#/push button/Wake
63	 *	[35]	MSS_GPIO[3]: MSS_PWDN
64	 *	[36]	MSS_GPIO[5]: MSS_VTT_EN
65	 *	[37-38]	I2C0
66	 *	[39]	PTP_CLK
67	 *	[40-41]	SATA[0/1]_PRESENT_ACTIVEn
68	 *	[42-43]	XG_MDC/XG_MDIO (XSMI)
69	 *	[44-55]	RGMII1
70	 *	[56-62]	SD
71	 */
72	/*   0    1    2    3    4    5    6    7    8    9 */
73	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
74		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
75		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
76		     0xff 0xff 0x7  0x0  0x7  0xa  0xa  0x2  0x2  0x5
77		     0x9  0x9  0x8  0x8  0x1  0x1  0x1  0x1  0x1  0x1
78		     0x1  0x1  0x1  0x1  0x1  0x1  0xe  0xe  0xe  0xe
79		     0xe  0xe  0xe>;
80};
81
82&cp0_comphy {
83	/* Serdes Configuration:
84	 *	Lane 0: PCIe0 (x1)
85	 *	Lane 1: SATA0
86	 *	Lane 2: SFI (10G)
87	 *	Lane 3: SATA1
88	 *	Lane 4: USB3_HOST1
89	 *	Lane 5: PCIe2 (x1)
90	 */
91	phy0 {
92		phy-type = <COMPHY_TYPE_PEX0>;
93	};
94	phy1 {
95		phy-type = <COMPHY_TYPE_SATA0>;
96	};
97	phy2 {
98		phy-type = <COMPHY_TYPE_SFI0>;
99	};
100	phy3 {
101		phy-type = <COMPHY_TYPE_SATA1>;
102	};
103	phy4 {
104		phy-type = <COMPHY_TYPE_USB3_HOST1>;
105	};
106	phy5 {
107		phy-type = <COMPHY_TYPE_PEX2>;
108	};
109};
110
111/* CON6 on CP0 expansion */
112&cp0_pcie0 {
113	status = "okay";
114};
115
116&cp0_pcie1 {
117	status = "disabled";
118};
119
120/* CON5 on CP0 expansion */
121&cp0_pcie2 {
122	status = "okay";
123};
124
125&cp0_i2c0 {
126	pinctrl-names = "default";
127	pinctrl-0 = <&cp0_i2c0_pins>;
128	status = "okay";
129	clock-frequency = <100000>;
130};
131
132/* CON4 on CP0 expansion */
133&cp0_sata0 {
134	status = "okay";
135};
136
137/* CON9 on CP0 expansion */
138&cp0_usb3_0 {
139	status = "okay";
140};
141
142/* CON10 on CP0 expansion */
143&cp0_usb3_1 {
144	status = "okay";
145};
146
147&cp0_utmi0 {
148	status = "okay";
149};
150
151&cp0_utmi1 {
152	status = "okay";
153};
154
155&cp0_sdhci0 {
156	pinctrl-names = "default";
157	pinctrl-0 = <&cp0_sdhci_pins>;
158	bus-width = <4>;
159	status = "okay";
160};
161
162&cp1_pinctl {
163	/* MPP Bus:
164	 *	[0-11]	RGMII0
165	 *	[13-16]	SPI1
166	 *	[27,31]	GE_MDIO/MDC
167	 *	[28]	SATA1_PRESENT_ACTIVEn
168	 *	[29-30]	UART0
169	 *	[32-62]	= 0xff: Keep default CP1_shared_pins
170	 */
171	/*   0    1    2    3    4    5    6    7    8    9 */
172	pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
173		     0x3  0x3  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
174		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0x9  0xa
175		     0xA  0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
176		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
177		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
178		     0xff 0xff 0xff>;
179};
180
181&cp1_comphy {
182	/* Serdes Configuration:
183	 *	Lane 0: PCIe0 (x1)
184	 *	Lane 1: SATA0
185	 *	Lane 2: SFI (10G)
186	 *	Lane 3: SATA1
187	 *	Lane 4: PCIe1 (x1)
188	 *	Lane 5: PCIe2 (x1)
189	 */
190	phy0 {
191		phy-type = <COMPHY_TYPE_PEX0>;
192	};
193	phy1 {
194		phy-type = <COMPHY_TYPE_SATA0>;
195	};
196	phy2 {
197		phy-type = <COMPHY_TYPE_SFI0>;
198	};
199	phy3 {
200		phy-type = <COMPHY_TYPE_SATA1>;
201	};
202	phy4 {
203		phy-type = <COMPHY_TYPE_PEX1>;
204	};
205	phy5 {
206		phy-type = <COMPHY_TYPE_PEX2>;
207	};
208};
209
210/* CON6 on CP1 expansion */
211&cp1_pcie0 {
212	status = "okay";
213};
214
215&cp1_pcie1 {
216	status = "okay";
217};
218
219/* CON5 on CP1 expansion */
220&cp1_pcie2 {
221	status = "okay";
222};
223
224&cp1_spi1 {
225	pinctrl-names = "default";
226	pinctrl-0 = <&cp1_spi1_pins>;
227	status = "okay";
228
229	spi-flash@0 {
230		#address-cells = <1>;
231		#size-cells = <1>;
232		compatible = "jedec,spi-nor";
233		reg = <0>;
234		spi-max-frequency = <10000000>;
235
236		partitions {
237			compatible = "fixed-partitions";
238			#address-cells = <1>;
239			#size-cells = <1>;
240
241			partition@0 {
242				label = "U-Boot";
243				reg = <0 0x200000>;
244			};
245			partition@400000 {
246				label = "Filesystem";
247				reg = <0x200000 0xce0000>;
248			};
249		};
250	};
251};
252
253/* CON4 on CP1 expansion */
254&cp1_sata0 {
255	status = "okay";
256};
257
258/* CON9 on CP1 expansion */
259&cp1_usb3_0 {
260	status = "okay";
261};
262
263/* CON10 on CP1 expansion */
264&cp1_usb3_1 {
265	status = "okay";
266};
267
268&cp1_utmi0 {
269	status = "okay";
270};
271
272&cp0_mdio {
273	phy1: ethernet-phy@1 {
274		reg = <1>;
275	};
276};
277
278&cp0_ethernet {
279	status = "okay";
280};
281
282&cp0_eth2 {
283	status = "okay";
284	phy = <&phy1>;
285	phy-mode = "rgmii-id";
286};
287