1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2016 - 2021 Marvell International Ltd.
4 */
5
6#include "armada-8040.dtsi" /* include SoC device tree */
7
8/ {
9	model = "MACCHIATOBin-8040";
10	compatible = "marvell,armada8040-mcbin",
11		     "marvell,armada8040";
12
13	chosen {
14		stdout-path = "serial0:115200n8";
15	};
16
17	aliases {
18		i2c0 = &cp0_i2c0;
19		i2c1 = &cp0_i2c1;
20		spi0 = &cp1_spi1;
21		gpio0 = &ap_gpio0;
22		gpio1 = &cp0_gpio0;
23		gpio2 = &cp0_gpio1;
24	};
25
26	memory@00000000 {
27		device_type = "memory";
28		reg = <0x0 0x0 0x0 0x80000000>;
29	};
30
31	simple-bus {
32		compatible = "simple-bus";
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		reg_usb3h0_vbus: usb3-vbus0 {
37			compatible = "regulator-fixed";
38			pinctrl-names = "default";
39			pinctrl-0 = <&cp0_xhci_vbus_pins>;
40			regulator-name = "reg-usb3h0-vbus";
41			regulator-min-microvolt = <5000000>;
42			regulator-max-microvolt = <5000000>;
43			startup-delay-us = <500000>;
44			enable-active-high;
45			regulator-always-on;
46			regulator-boot-on;
47			gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
48		};
49	};
50};
51
52/* Accessible over the mini-USB CON9 connector on the main board */
53&uart0 {
54	status = "okay";
55};
56
57&ap_pinctl {
58	/*
59	 * MPP Bus:
60	 * eMMC [0-10]
61	 * UART0 [11,19]
62	 */
63		  /* 0 1 2 3 4 5 6 7 8 9 */
64	pin-func = < 1 1 1 1 1 1 1 1 1 1
65		     1 3 0 0 0 0 0 0 0 3 >;
66};
67
68/* on-board eMMC */
69&ap_sdhci0 {
70	pinctrl-names = "default";
71	pinctrl-0 = <&ap_emmc_pins>;
72	bus-width= <8>;
73	status = "okay";
74};
75
76&cp0_pinctl {
77	/*
78	 * MPP Bus:
79	 * [0-31] = 0xff: Keep default CP0_shared_pins:
80	 * [11] CLKOUT_MPP_11 (out)
81	 * [23] LINK_RD_IN_CP2CP (in)
82	 * [25] CLKOUT_MPP_25 (out)
83	 * [29] AVS_FB_IN_CP2CP (in)
84	 * [32,34] SMI
85	 * [33]    MSS power down
86	 * [35-38] CP0 I2C1 and I2C0
87	 * [39] MSS CKE Enable
88	 * [40,41] CP0 UART1 TX/RX
89	 * [42,43] XSMI (controls two 10G phys)
90	 * [47] USB VBUS EN
91	 * [48] FAN PWM
92	 * [49] 10G port 1 interrupt
93	 * [50] 10G port 0 interrupt
94	 * [51] 2.5G SFP TX fault
95	 * [52] PCIe reset out
96	 * [53] 2.5G SFP mode
97	 * [54] 2.5G SFP LOS
98	 * [55] Micro SD card detect
99	 * [56-61] Micro SD
100	 * [62] CP1 SFI SFP FAULT
101	 */
102		/*   0    1    2    3    4    5    6    7    8    9 */
103	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
104		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
105		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
106		     0xff 0    7    0xa  7    2    2    2    2    0xa
107		     7    7    8    8    0    0    0    0    0    0
108		     0    0    0    0    0    0    0xe  0xe  0xe  0xe
109		     0xe  0xe  0 >;
110
111	cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
112		marvell,pins = < 47 >;
113		marvell,function = <0>;
114	};
115
116	cp0_pcie_reset_pins: cp0-pcie-reset-pins {
117		marvell,pins = < 52 >;
118		marvell,function = <0>;
119	};
120};
121
122/* uSD slot */
123&cp0_sdhci0 {
124	pinctrl-names = "default";
125	pinctrl-0 = <&cp0_sdhci_pins>;
126	bus-width= <4>;
127	status = "okay";
128};
129
130/* PCIe x4 */
131&cp0_pcie0 {
132	num-lanes = <4>;
133	pinctrl-names = "default";
134	pinctrl-0 = <&cp0_pcie_reset_pins>;
135	marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
136	status = "okay";
137};
138
139&cp0_i2c0 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&cp0_i2c0_pins>;
142	status = "okay";
143	clock-frequency = <100000>;
144};
145
146&cp0_i2c1 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&cp0_i2c1_pins>;
149	status = "okay";
150	clock-frequency = <100000>;
151};
152
153&cp0_sata0 {
154	status = "okay";
155};
156
157&cp0_mdio {
158	ge_phy: ethernet-phy@0 {
159		reg = <0>;
160	};
161};
162
163&cp0_comphy {
164	/*
165	 * CP0 Serdes Configuration:
166	 * Lane 0: PCIe0 (x4)
167	 * Lane 1: PCIe0 (x4)
168	 * Lane 2: PCIe0 (x4)
169	 * Lane 3: PCIe0 (x4)
170	 * Lane 4: SFI (10G)
171	 * Lane 5: SATA1
172	 */
173	phy0 {
174		phy-type = <COMPHY_TYPE_PEX0>;
175	};
176	phy1 {
177		phy-type = <COMPHY_TYPE_PEX0>;
178	};
179	phy2 {
180		phy-type = <COMPHY_TYPE_PEX0>;
181	};
182	phy3 {
183		phy-type = <COMPHY_TYPE_PEX0>;
184	};
185	phy4 {
186		phy-type = <COMPHY_TYPE_SFI0>;
187	};
188	phy5 {
189		phy-type = <COMPHY_TYPE_SATA1>;
190	};
191};
192
193&cp1_sata0 {
194	status = "okay";
195};
196
197&cp1_usb3_0 {
198	vbus-supply = <&reg_usb3h0_vbus>;
199	status = "okay";
200};
201
202&cp1_utmi0 {
203	status = "okay";
204};
205
206&cp1_ethernet {
207	status = "okay";
208};
209
210&cp1_eth1 {
211	status = "okay";
212	phy = <&ge_phy>;
213	phy-mode = "sgmii";
214};
215
216&cp1_pinctl {
217	/*
218	 * MPP Bus:
219	 * [0-5] TDM
220	 * [6,7] CP1_UART 0
221	 * [8]   CP1 10G SFP LOS
222	 * [9]   CP1 10G PHY RESET
223	 * [10]  CP1 10G SFP TX Disable
224	 * [11]  CP1 10G SFP Mode
225	 * [12]  SPI1 CS1n
226	 * [13]  SPI1 MISO (TDM and SPI ROM shared)
227	 * [14]  SPI1 CS0n
228	 * [15]  SPI1 MOSI (TDM and SPI ROM shared)
229	 * [16]  SPI1 CLK (TDM and SPI ROM shared)
230	 * [24]  CP1 2.5G SFP TX Disable
231	 * [26]  CP0 10G SFP TX Fault
232	 * [27]  CP0 10G SFP Mode
233	 * [28]  CP0 10G SFP LOS
234	 * [29]  CP0 10G SFP TX Disable
235	 * [30]  USB Over current indication
236	 * [31]  10G Port 0 phy reset
237	 * [32-62] = 0xff: Keep default CP1_shared_pins:
238	 */
239		/*   0    1    2    3    4    5    6    7    8    9 */
240	pin-func = < 0x4  0x4  0x4  0x4  0x4  0x4  0x8  0x8  0x0  0x0
241		     0x0  0x0  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
242		     0xff 0xff 0xff 0xff 0x0  0xff 0x0  0x0  0x0 0x0
243		     0x0  0x0  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
244		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
245		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
246		     0xff 0xff 0xff>;
247};
248
249&cp1_spi1 {
250	pinctrl-names = "default";
251	pinctrl-0 = <&cp1_spi1_pins>;
252	status = "okay";
253
254	spi-flash@0 {
255		#address-cells = <1>;
256		#size-cells = <1>;
257		compatible = "jedec,spi-nor";
258		reg = <0>;
259		spi-max-frequency = <10000000>;
260
261		partitions {
262			compatible = "fixed-partitions";
263			#address-cells = <1>;
264			#size-cells = <1>;
265
266			partition@0 {
267				label = "U-Boot";
268				reg = <0 0x200000>;
269			};
270			partition@400000 {
271				label = "Filesystem";
272				reg = <0x200000 0xce0000>;
273			};
274		};
275	};
276};
277
278&cp1_comphy {
279	/*
280	 * CP1 Serdes Configuration:
281	 * Lane 0: SGMII1
282	 * Lane 1: SATA 0
283	 * Lane 2: USB HOST 0
284	 * Lane 3: SATA1
285	 * Lane 4: SFI (10G)
286	 * Lane 5: SGMII3
287	 */
288	phy0 {
289		phy-type = <COMPHY_TYPE_SGMII1>;
290		phy-speed = <COMPHY_SPEED_1_25G>;
291	};
292	phy1 {
293		phy-type = <COMPHY_TYPE_SATA0>;
294	};
295	phy2 {
296		phy-type = <COMPHY_TYPE_USB3_HOST0>;
297	};
298	phy3 {
299		phy-type = <COMPHY_TYPE_SATA1>;
300	};
301	phy4 {
302		phy-type = <COMPHY_TYPE_SFI0>;
303	};
304	phy5 {
305		phy-type = <COMPHY_TYPE_SGMII2>;
306		phy-speed = <COMPHY_SPEED_3_125G>;
307	};
308};
309