1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 *
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
14 */
15
16#include "armada-370-xp.dtsi"
17
18/ {
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	model = "Marvell Armada XP family SoC";
23	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25	aliases {
26		serial2 = &uart2;
27		serial3 = &uart3;
28	};
29
30	soc {
31		compatible = "marvell,armadaxp-mbus", "simple-bus";
32		u-boot,dm-pre-reloc;
33
34		bootrom {
35			compatible = "marvell,bootrom";
36			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
37		};
38
39		internal-regs {
40			sdramc: sdramc@1400 {
41				compatible = "marvell,armada-xp-sdram-controller";
42				reg = <0x1400 0x500>;
43			};
44
45			L2: l2-cache@8000 {
46				compatible = "marvell,aurora-system-cache";
47				reg = <0x08000 0x1000>;
48				cache-id-part = <0x100>;
49				cache-level = <2>;
50				cache-unified;
51				wt-override;
52			};
53
54			uart2: serial@12200 {
55				compatible = "snps,dw-apb-uart";
56				pinctrl-0 = <&uart2_pins>;
57				pinctrl-names = "default";
58				reg = <0x12200 0x100>;
59				reg-shift = <2>;
60				interrupts = <43>;
61				reg-io-width = <1>;
62				clocks = <&coreclk 0>;
63				status = "disabled";
64			};
65
66			uart3: serial@12300 {
67				compatible = "snps,dw-apb-uart";
68				pinctrl-0 = <&uart3_pins>;
69				pinctrl-names = "default";
70				reg = <0x12300 0x100>;
71				reg-shift = <2>;
72				interrupts = <44>;
73				reg-io-width = <1>;
74				clocks = <&coreclk 0>;
75				status = "disabled";
76			};
77
78			systemc: system-controller@18200 {
79				compatible = "marvell,armada-370-xp-system-controller";
80				reg = <0x18200 0x500>;
81			};
82
83			gateclk: clock-gating-control@18220 {
84				compatible = "marvell,armada-xp-gating-clock";
85				reg = <0x18220 0x4>;
86				clocks = <&coreclk 0>;
87				#clock-cells = <1>;
88			};
89
90			coreclk: mvebu-sar@18230 {
91				compatible = "marvell,armada-xp-core-clock";
92				reg = <0x18230 0x08>;
93				#clock-cells = <1>;
94			};
95
96			thermal: thermal@182b0 {
97				compatible = "marvell,armadaxp-thermal";
98				reg = <0x182b0 0x4
99					0x184d0 0x4>;
100				status = "okay";
101			};
102
103			cpuclk: clock-complex@18700 {
104				#clock-cells = <1>;
105				compatible = "marvell,armada-xp-cpu-clock";
106				reg = <0x18700 0x24>, <0x1c054 0x10>;
107				clocks = <&coreclk 1>;
108			};
109
110			cpu-config@21000 {
111				compatible = "marvell,armada-xp-cpu-config";
112				reg = <0x21000 0x8>;
113			};
114
115			eth2: ethernet@30000 {
116				compatible = "marvell,armada-xp-neta";
117				reg = <0x30000 0x4000>;
118				interrupts = <12>;
119				clocks = <&gateclk 2>;
120				status = "disabled";
121			};
122
123			usb2: usb@52000 {
124				compatible = "marvell,orion-ehci";
125				reg = <0x52000 0x500>;
126				interrupts = <47>;
127				clocks = <&gateclk 20>;
128				status = "disabled";
129			};
130
131			xor1: xor@60900 {
132				compatible = "marvell,orion-xor";
133				reg = <0x60900 0x100
134				       0x60b00 0x100>;
135				clocks = <&gateclk 22>;
136				status = "okay";
137
138				xor10 {
139					interrupts = <51>;
140					dmacap,memcpy;
141					dmacap,xor;
142				};
143				xor11 {
144					interrupts = <52>;
145					dmacap,memcpy;
146					dmacap,xor;
147					dmacap,memset;
148				};
149			};
150
151			ethernet@70000 {
152				compatible = "marvell,armada-xp-neta";
153			};
154
155			ethernet@74000 {
156				compatible = "marvell,armada-xp-neta";
157			};
158
159			cesa: crypto@90000 {
160				compatible = "marvell,armada-xp-crypto";
161				reg = <0x90000 0x10000>;
162				reg-names = "regs";
163				interrupts = <48>, <49>;
164				clocks = <&gateclk 23>, <&gateclk 23>;
165				clock-names = "cesa0", "cesa1";
166				marvell,crypto-srams = <&crypto_sram0>,
167						       <&crypto_sram1>;
168				marvell,crypto-sram-size = <0x800>;
169			};
170
171			bm: bm@c0000 {
172				compatible = "marvell,armada-380-neta-bm";
173				reg = <0xc0000 0xac>;
174				clocks = <&gateclk 13>;
175				internal-mem = <&bm_bppi>;
176				status = "disabled";
177			};
178
179			xor0: xor@f0900 {
180				compatible = "marvell,orion-xor";
181				reg = <0xF0900 0x100
182				       0xF0B00 0x100>;
183				clocks = <&gateclk 28>;
184				status = "okay";
185
186				xor00 {
187					interrupts = <94>;
188					dmacap,memcpy;
189					dmacap,xor;
190				};
191				xor01 {
192					interrupts = <95>;
193					dmacap,memcpy;
194					dmacap,xor;
195					dmacap,memset;
196				};
197			};
198		};
199
200		crypto_sram0: sa-sram0 {
201			compatible = "mmio-sram";
202			reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
203			clocks = <&gateclk 23>;
204			#address-cells = <1>;
205			#size-cells = <1>;
206			ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
207		};
208
209		crypto_sram1: sa-sram1 {
210			compatible = "mmio-sram";
211			reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
212			clocks = <&gateclk 23>;
213			#address-cells = <1>;
214			#size-cells = <1>;
215			ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
216		};
217
218		bm_bppi: bm-bppi {
219			compatible = "mmio-sram";
220			reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
221			ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
222			#address-cells = <1>;
223			#size-cells = <1>;
224			clocks = <&gateclk 13>;
225			no-memory-wc;
226			status = "disabled";
227		};
228	};
229
230	clocks {
231		/* 25 MHz reference crystal */
232		refclk: oscillator {
233			compatible = "fixed-clock";
234			#clock-cells = <0>;
235			clock-frequency = <25000000>;
236		};
237	};
238};
239
240&i2c0 {
241	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
242	reg = <0x11000 0x100>;
243};
244
245&i2c1 {
246	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
247	reg = <0x11100 0x100>;
248};
249
250&mpic {
251	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
252};
253
254&timer {
255	compatible = "marvell,armada-xp-timer";
256	clocks = <&coreclk 2>, <&refclk>;
257	clock-names = "nbclk", "fixed";
258};
259
260&watchdog {
261	compatible = "marvell,armada-xp-wdt";
262	clocks = <&coreclk 2>, <&refclk>;
263	clock-names = "nbclk", "fixed";
264};
265
266&cpurst {
267	reg = <0x20800 0x20>;
268};
269
270&usb0 {
271	clocks = <&gateclk 18>;
272};
273
274&usb1 {
275	clocks = <&gateclk 19>;
276};
277
278&pinctrl {
279	ge0_gmii_pins: ge0-gmii-pins {
280		marvell,pins =
281		     "mpp0",  "mpp1",  "mpp2",  "mpp3",
282		     "mpp4",  "mpp5",  "mpp6",  "mpp7",
283		     "mpp8",  "mpp9",  "mpp10", "mpp11",
284		     "mpp12", "mpp13", "mpp14", "mpp15",
285		     "mpp16", "mpp17", "mpp18", "mpp19",
286		     "mpp20", "mpp21", "mpp22", "mpp23";
287		marvell,function = "ge0";
288	};
289
290	ge0_rgmii_pins: ge0-rgmii-pins {
291		marvell,pins =
292		     "mpp0", "mpp1", "mpp2", "mpp3",
293		     "mpp4", "mpp5", "mpp6", "mpp7",
294		     "mpp8", "mpp9", "mpp10", "mpp11";
295		marvell,function = "ge0";
296	};
297
298	ge1_rgmii_pins: ge1-rgmii-pins {
299		marvell,pins =
300		     "mpp12", "mpp13", "mpp14", "mpp15",
301		     "mpp16", "mpp17", "mpp18", "mpp19",
302		     "mpp20", "mpp21", "mpp22", "mpp23";
303		marvell,function = "ge1";
304	};
305
306	sdio_pins: sdio-pins {
307		marvell,pins = "mpp30", "mpp31", "mpp32",
308			       "mpp33", "mpp34", "mpp35";
309		marvell,function = "sd0";
310	};
311
312	spi0_pins: spi0-pins {
313		marvell,pins = "mpp36", "mpp37",
314			       "mpp38", "mpp39";
315		marvell,function = "spi0";
316	};
317
318	spi1_pins: spi1-pins {
319		marvell,pins = "mpp13", "mpp14",
320			       "mpp16", "mpp17";
321		marvell,function = "spi1";
322	};
323
324	uart2_pins: uart2-pins {
325		marvell,pins = "mpp42", "mpp43";
326		marvell,function = "uart2";
327	};
328
329	uart3_pins: uart3-pins {
330		marvell,pins = "mpp44", "mpp45";
331		marvell,function = "uart3";
332	};
333};
334
335&spi0 {
336	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
337	pinctrl-0 = <&spi0_pins>;
338	pinctrl-names = "default";
339};
340
341&spi1 {
342	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
343	pinctrl-0 = <&spi1_pins>;
344	pinctrl-names = "default";
345};
346