1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2018 Marvell International Ltd. 4 */ 5 6/* 7 * Device Tree file for the CN 9030 SoC, made of an AP806 Quad and 8 * one CP110. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include "armada-common.dtsi" 13#include "armada-ap807.dtsi" 14#include "armada-ap80x-quad.dtsi" 15 16/* This defines used to calculate the base address of each CP */ 17#define CP110_BASE_OFFSET (0xf2000000) 18#define CP110_SPACE_SIZE (0x02000000) 19#define CP110_BASE (CP110_BASE_OFFSET + \ 20 (CP110_NUM * CP110_SPACE_SIZE)) 21 22#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) 23#define CP110_PCIE_BUS_MEM_CFG (0x82000000) 24 25/* CP110-0 Settings */ 26#define CP110_NAME cp0 27#define CP110_NUM 0 28#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ 29 (0xe0000000 + (iface - 1) * 0x1000000)) 30#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface)) 31 32#include "armada-cp110.dtsi" 33 34/ { 35 model = "Marvell CN 9030"; 36 compatible = "marvell,armada70x0", "marvell,armada-ap806-quad", 37 "marvell,armada-ap806"; 38}; 39 40&cp0_pinctl { 41 compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl"; 42 bank-name ="cp0-110"; 43 44 cp0_i2c0_pins: cp0-i2c-pins-0 { 45 marvell,pins = < 37 38 >; 46 marvell,function = <2>; 47 }; 48 cp0_i2c1_pins: cp0-i2c-pins-1 { 49 marvell,pins = < 35 36 >; 50 marvell,function = <2>; 51 }; 52 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 { 53 marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>; 54 marvell,function = <3>; 55 }; 56 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 { 57 marvell,pins = < 44 45 46 47 48 49 50 51 58 52 53 54 55 >; 59 marvell,function = <1>; 60 }; 61 cp0_pca0_pins: cp0-pca0_pins { 62 marvell,pins = <62>; 63 marvell,function = <0>; 64 }; 65 cp0_sdhci_pins: cp0-sdhi-pins-0 { 66 marvell,pins = < 56 57 58 59 60 61 >; 67 marvell,function = <14>; 68 }; 69 cp0_spi0_pins: cp0-spi-pins-0 { 70 marvell,pins = < 13 14 15 16 >; 71 marvell,function = <3>; 72 }; 73}; 74