1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx7d.dtsi" 9 10/ { 11 model = "Freescale i.MX7 SabreSD Board"; 12 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 13 14 chosen { 15 stdout-path = &uart1; 16 }; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x80000000 0x80000000>; 21 }; 22 23 gpio-keys { 24 compatible = "gpio-keys"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_gpio_keys>; 27 28 volume-up { 29 label = "Volume Up"; 30 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 31 linux,code = <KEY_VOLUMEUP>; 32 wakeup-source; 33 }; 34 35 volume-down { 36 label = "Volume Down"; 37 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 38 linux,code = <KEY_VOLUMEDOWN>; 39 wakeup-source; 40 }; 41 }; 42 43 spi4 { 44 compatible = "spi-gpio"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_spi4>; 47 gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>; 48 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>; 49 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 50 num-chipselects = <1>; 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 extended_io: gpio-expander@0 { 55 compatible = "fairchild,74hc595"; 56 gpio-controller; 57 #gpio-cells = <2>; 58 reg = <0>; 59 registers-number = <1>; 60 spi-max-frequency = <100000>; 61 }; 62 }; 63 64 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 65 compatible = "regulator-fixed"; 66 regulator-name = "usb_otg1_vbus"; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 70 enable-active-high; 71 }; 72 73 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 74 compatible = "regulator-fixed"; 75 regulator-name = "usb_otg2_vbus"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 81 enable-active-high; 82 }; 83 84 reg_vref_1v8: regulator-vref-1v8 { 85 compatible = "regulator-fixed"; 86 regulator-name = "vref-1v8"; 87 regulator-min-microvolt = <1800000>; 88 regulator-max-microvolt = <1800000>; 89 }; 90 91 reg_brcm: regulator-brcm { 92 compatible = "regulator-fixed"; 93 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 94 enable-active-high; 95 regulator-name = "brcm_reg"; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_brcm_reg>; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 startup-delay-us = <200000>; 101 }; 102 103 reg_lcd_3v3: regulator-lcd-3v3 { 104 compatible = "regulator-fixed"; 105 regulator-name = "lcd-3v3"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 109 }; 110 111 reg_can2_3v3: regulator-can2-3v3 { 112 compatible = "regulator-fixed"; 113 regulator-name = "can2-3v3"; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_flexcan2_reg>; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 119 }; 120 121 reg_fec2_3v3: regulator-fec2-3v3 { 122 compatible = "regulator-fixed"; 123 regulator-name = "fec2-3v3"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_enet2_reg>; 126 regulator-min-microvolt = <3300000>; 127 regulator-max-microvolt = <3300000>; 128 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; 129 }; 130 131 backlight: backlight { 132 compatible = "pwm-backlight"; 133 pwms = <&pwm1 0 5000000 0>; 134 brightness-levels = <0 4 8 16 32 64 128 255>; 135 default-brightness-level = <6>; 136 status = "okay"; 137 }; 138 139 panel { 140 compatible = "innolux,at043tn24"; 141 backlight = <&backlight>; 142 power-supply = <®_lcd_3v3>; 143 144 port { 145 panel_in: endpoint { 146 remote-endpoint = <&display_out>; 147 }; 148 }; 149 }; 150}; 151 152&adc1 { 153 vref-supply = <®_vref_1v8>; 154 status = "okay"; 155}; 156 157&adc2 { 158 vref-supply = <®_vref_1v8>; 159 status = "okay"; 160}; 161 162&cpu0 { 163 cpu-supply = <&sw1a_reg>; 164}; 165 166&ecspi3 { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_ecspi3>; 169 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 170 status = "okay"; 171 172 tsc2046@0 { 173 compatible = "ti,tsc2046"; 174 reg = <0>; 175 spi-max-frequency = <1000000>; 176 pinctrl-names ="default"; 177 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 178 interrupt-parent = <&gpio2>; 179 interrupts = <29 0>; 180 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 181 ti,x-min = /bits/ 16 <0>; 182 ti,x-max = /bits/ 16 <0>; 183 ti,y-min = /bits/ 16 <0>; 184 ti,y-max = /bits/ 16 <0>; 185 ti,pressure-max = /bits/ 16 <0>; 186 ti,x-plate-ohms = /bits/ 16 <400>; 187 wakeup-source; 188 }; 189}; 190 191&fec1 { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_enet1>; 194 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 195 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 196 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 197 assigned-clock-rates = <0>, <100000000>; 198 phy-mode = "rgmii"; 199 phy-handle = <ðphy0>; 200 fsl,magic-packet; 201 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 202 status = "okay"; 203 204 mdio { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 ethphy0: ethernet-phy@0 { 209 reg = <0>; 210 }; 211 212 ethphy1: ethernet-phy@1 { 213 reg = <1>; 214 }; 215 }; 216}; 217 218&fec2 { 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_enet2>; 221 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 222 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 223 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 224 assigned-clock-rates = <0>, <100000000>; 225 phy-mode = "rgmii"; 226 phy-handle = <ðphy1>; 227 phy-supply = <®_fec2_3v3>; 228 fsl,magic-packet; 229 status = "okay"; 230}; 231 232&flexcan2 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_flexcan2>; 235 xceiver-supply = <®_can2_3v3>; 236 status = "okay"; 237}; 238 239&i2c1 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_i2c1>; 242 status = "okay"; 243 244 pmic: pfuze3000@8 { 245 compatible = "fsl,pfuze3000"; 246 reg = <0x08>; 247 248 regulators { 249 sw1a_reg: sw1a { 250 regulator-min-microvolt = <700000>; 251 regulator-max-microvolt = <1475000>; 252 regulator-boot-on; 253 regulator-always-on; 254 regulator-ramp-delay = <6250>; 255 }; 256 257 /* use sw1c_reg to align with pfuze100/pfuze200 */ 258 sw1c_reg: sw1b { 259 regulator-min-microvolt = <700000>; 260 regulator-max-microvolt = <1475000>; 261 regulator-boot-on; 262 regulator-always-on; 263 regulator-ramp-delay = <6250>; 264 }; 265 266 sw2_reg: sw2 { 267 regulator-min-microvolt = <1800000>; 268 regulator-max-microvolt = <1800000>; 269 regulator-boot-on; 270 regulator-always-on; 271 }; 272 273 sw3a_reg: sw3 { 274 regulator-min-microvolt = <900000>; 275 regulator-max-microvolt = <1650000>; 276 regulator-boot-on; 277 regulator-always-on; 278 }; 279 280 swbst_reg: swbst { 281 regulator-min-microvolt = <5000000>; 282 regulator-max-microvolt = <5150000>; 283 }; 284 285 snvs_reg: vsnvs { 286 regulator-min-microvolt = <1000000>; 287 regulator-max-microvolt = <3000000>; 288 regulator-boot-on; 289 regulator-always-on; 290 }; 291 292 vref_reg: vrefddr { 293 regulator-boot-on; 294 regulator-always-on; 295 }; 296 297 vgen1_reg: vldo1 { 298 regulator-min-microvolt = <1800000>; 299 regulator-max-microvolt = <3300000>; 300 regulator-always-on; 301 }; 302 303 vgen2_reg: vldo2 { 304 regulator-min-microvolt = <800000>; 305 regulator-max-microvolt = <1550000>; 306 }; 307 308 vgen3_reg: vccsd { 309 regulator-min-microvolt = <2850000>; 310 regulator-max-microvolt = <3300000>; 311 regulator-always-on; 312 }; 313 314 vgen4_reg: v33 { 315 regulator-min-microvolt = <2850000>; 316 regulator-max-microvolt = <3300000>; 317 regulator-always-on; 318 }; 319 320 vgen5_reg: vldo3 { 321 regulator-min-microvolt = <1800000>; 322 regulator-max-microvolt = <3300000>; 323 regulator-always-on; 324 }; 325 326 vgen6_reg: vldo4 { 327 regulator-min-microvolt = <2800000>; 328 regulator-max-microvolt = <2800000>; 329 regulator-always-on; 330 }; 331 }; 332 }; 333}; 334 335&i2c2 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_i2c2>; 338 status = "okay"; 339 340 mpl3115@60 { 341 compatible = "fsl,mpl3115"; 342 reg = <0x60>; 343 }; 344}; 345 346&i2c3 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_i2c3>; 349 status = "okay"; 350}; 351 352&i2c4 { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_i2c4>; 355 status = "okay"; 356 357 codec: wm8960@1a { 358 compatible = "wlf,wm8960"; 359 reg = <0x1a>; 360 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 361 clock-names = "mclk"; 362 wlf,shared-lrclk; 363 }; 364}; 365 366&lcdif { 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_lcdif>; 369 status = "okay"; 370 371 port { 372 display_out: endpoint { 373 remote-endpoint = <&panel_in>; 374 }; 375 }; 376}; 377 378&snvs_pwrkey { 379 status = "okay"; 380}; 381 382&uart1 { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_uart1>; 385 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 386 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 387 status = "okay"; 388}; 389 390&uart6 { 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_uart6>; 393 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 394 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 395 uart-has-rtscts; 396 status = "okay"; 397}; 398 399&usbotg1 { 400 vbus-supply = <®_usb_otg1_vbus>; 401 status = "okay"; 402}; 403 404&usbotg2 { 405 vbus-supply = <®_usb_otg2_vbus>; 406 dr_mode = "host"; 407 status = "okay"; 408}; 409 410&usdhc1 { 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pinctrl_usdhc1>; 413 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 414 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 415 wakeup-source; 416 keep-power-in-suspend; 417 status = "okay"; 418}; 419 420&usdhc2 { 421 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 422 pinctrl-0 = <&pinctrl_usdhc2>; 423 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 424 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 425 wakeup-source; 426 keep-power-in-suspend; 427 non-removable; 428 vmmc-supply = <®_brcm>; 429 fsl,tuning-step = <2>; 430 status = "okay"; 431}; 432 433&usdhc3 { 434 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 435 pinctrl-0 = <&pinctrl_usdhc3>; 436 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 437 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 438 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 439 assigned-clock-rates = <400000000>; 440 bus-width = <8>; 441 fsl,tuning-step = <2>; 442 non-removable; 443 status = "okay"; 444}; 445 446&wdog1 { 447 pinctrl-names = "default"; 448 pinctrl-0 = <&pinctrl_wdog>; 449 fsl,ext-reset-output; 450}; 451 452&iomuxc { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_hog>; 455 456 imx7d-sdb { 457 pinctrl_brcm_reg: brcmreggrp { 458 fsl,pins = < 459 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 460 >; 461 }; 462 463 pinctrl_ecspi3: ecspi3grp { 464 fsl,pins = < 465 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 466 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 467 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 468 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 469 >; 470 }; 471 472 pinctrl_enet1: enet1grp { 473 fsl,pins = < 474 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 475 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 476 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 477 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 478 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 479 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 480 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 481 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 482 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 483 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 484 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 485 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 486 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 487 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 488 >; 489 }; 490 491 pinctrl_enet2: enet2grp { 492 fsl,pins = < 493 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 494 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 495 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 496 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 497 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 498 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 499 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 500 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 501 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 502 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 503 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 504 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 505 >; 506 }; 507 508 pinctrl_enet2_reg: enet2reggrp { 509 fsl,pins = < 510 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 511 >; 512 }; 513 514 pinctrl_flexcan2: flexcan2grp { 515 fsl,pins = < 516 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 517 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 518 >; 519 }; 520 521 pinctrl_flexcan2_reg: flexcan2reggrp { 522 fsl,pins = < 523 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 524 >; 525 }; 526 527 pinctrl_gpio_keys: gpio_keysgrp { 528 fsl,pins = < 529 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 530 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 531 >; 532 }; 533 534 pinctrl_hog: hoggrp { 535 fsl,pins = < 536 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 537 >; 538 }; 539 540 pinctrl_i2c1: i2c1grp { 541 fsl,pins = < 542 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 543 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 544 >; 545 }; 546 547 pinctrl_i2c2: i2c2grp { 548 fsl,pins = < 549 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 550 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 551 >; 552 }; 553 554 pinctrl_i2c3: i2c3grp { 555 fsl,pins = < 556 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 557 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 558 >; 559 }; 560 561 pinctrl_i2c4: i2c4grp { 562 fsl,pins = < 563 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 564 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 565 >; 566 }; 567 568 pinctrl_lcdif: lcdifgrp { 569 fsl,pins = < 570 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 571 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 572 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 573 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 574 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 575 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 576 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 577 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 578 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 579 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 580 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 581 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 582 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 583 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 584 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 585 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 586 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 587 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 588 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 589 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 590 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 591 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 592 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 593 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 594 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 595 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 596 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 597 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 598 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 599 >; 600 }; 601 602 pinctrl_spi4: spi4grp { 603 fsl,pins = < 604 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 605 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 606 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 607 >; 608 }; 609 610 pinctrl_tsc2046_pendown: tsc2046_pendown { 611 fsl,pins = < 612 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 613 >; 614 }; 615 616 pinctrl_uart1: uart1grp { 617 fsl,pins = < 618 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 619 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 620 >; 621 }; 622 623 pinctrl_uart5: uart5grp { 624 fsl,pins = < 625 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 626 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 627 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 628 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 629 >; 630 }; 631 632 pinctrl_uart6: uart6grp { 633 fsl,pins = < 634 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 635 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 636 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 637 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 638 >; 639 }; 640 641 pinctrl_usdhc1: usdhc1grp { 642 fsl,pins = < 643 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 644 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 645 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 646 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 647 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 648 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 649 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 650 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 651 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 652 >; 653 }; 654 655 pinctrl_usdhc2: usdhc2grp { 656 fsl,pins = < 657 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 658 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 659 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 660 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 661 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 662 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 663 >; 664 }; 665 666 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 667 fsl,pins = < 668 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 669 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 670 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 671 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 672 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 673 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 674 >; 675 }; 676 677 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 678 fsl,pins = < 679 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 680 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 681 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 682 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 683 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 684 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 685 >; 686 }; 687 688 689 pinctrl_usdhc3: usdhc3grp { 690 fsl,pins = < 691 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 692 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 693 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 694 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 695 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 696 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 697 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 698 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 699 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 700 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 701 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 702 >; 703 }; 704 705 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 706 fsl,pins = < 707 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 708 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 709 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 710 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 711 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 712 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 713 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 714 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 715 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 716 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 717 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 718 >; 719 }; 720 721 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 722 fsl,pins = < 723 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 724 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 725 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 726 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 727 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 728 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 729 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 730 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 731 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 732 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 733 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 734 >; 735 }; 736 }; 737}; 738 739&pwm1 { 740 pinctrl-names = "default"; 741 pinctrl-0 = <&pinctrl_pwm1>; 742 status = "okay"; 743}; 744 745&iomuxc_lpsr { 746 pinctrl_wdog: wdoggrp { 747 fsl,pins = < 748 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 749 >; 750 }; 751 752 pinctrl_pwm1: pwm1grp { 753 fsl,pins = < 754 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 755 >; 756 }; 757 758 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { 759 fsl,pins = < 760 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 761 >; 762 }; 763}; 764