1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/power/imx8mm-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mm-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; /* two CLK32 periods */ 66 clocks = <&clk IMX8MM_CLK_ARM>; 67 enable-method = "psci"; 68 next-level-cache = <&A53_L2>; 69 operating-points-v2 = <&a53_opp_table>; 70 nvmem-cells = <&cpu_speed_grade>; 71 nvmem-cell-names = "speed_grade"; 72 cpu-idle-states = <&cpu_pd_wait>; 73 #cooling-cells = <2>; 74 }; 75 76 A53_1: cpu@1 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x1>; 80 clock-latency = <61036>; /* two CLK32 periods */ 81 clocks = <&clk IMX8MM_CLK_ARM>; 82 enable-method = "psci"; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 cpu-idle-states = <&cpu_pd_wait>; 86 #cooling-cells = <2>; 87 }; 88 89 A53_2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x2>; 93 clock-latency = <61036>; /* two CLK32 periods */ 94 clocks = <&clk IMX8MM_CLK_ARM>; 95 enable-method = "psci"; 96 next-level-cache = <&A53_L2>; 97 operating-points-v2 = <&a53_opp_table>; 98 cpu-idle-states = <&cpu_pd_wait>; 99 #cooling-cells = <2>; 100 }; 101 102 A53_3: cpu@3 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x3>; 106 clock-latency = <61036>; /* two CLK32 periods */ 107 clocks = <&clk IMX8MM_CLK_ARM>; 108 enable-method = "psci"; 109 next-level-cache = <&A53_L2>; 110 operating-points-v2 = <&a53_opp_table>; 111 cpu-idle-states = <&cpu_pd_wait>; 112 #cooling-cells = <2>; 113 }; 114 115 A53_L2: l2-cache0 { 116 compatible = "cache"; 117 }; 118 }; 119 120 a53_opp_table: opp-table { 121 compatible = "operating-points-v2"; 122 opp-shared; 123 124 opp-1200000000 { 125 opp-hz = /bits/ 64 <1200000000>; 126 opp-microvolt = <850000>; 127 opp-supported-hw = <0xe>, <0x7>; 128 clock-latency-ns = <150000>; 129 opp-suspend; 130 }; 131 132 opp-1600000000 { 133 opp-hz = /bits/ 64 <1600000000>; 134 opp-microvolt = <950000>; 135 opp-supported-hw = <0xc>, <0x7>; 136 clock-latency-ns = <150000>; 137 opp-suspend; 138 }; 139 140 opp-1800000000 { 141 opp-hz = /bits/ 64 <1800000000>; 142 opp-microvolt = <1000000>; 143 opp-supported-hw = <0x8>, <0x3>; 144 clock-latency-ns = <150000>; 145 opp-suspend; 146 }; 147 }; 148 149 osc_32k: clock-osc-32k { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <32768>; 153 clock-output-names = "osc_32k"; 154 }; 155 156 osc_24m: clock-osc-24m { 157 compatible = "fixed-clock"; 158 #clock-cells = <0>; 159 clock-frequency = <24000000>; 160 clock-output-names = "osc_24m"; 161 }; 162 163 clk_ext1: clock-ext1 { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <133000000>; 167 clock-output-names = "clk_ext1"; 168 }; 169 170 clk_ext2: clock-ext2 { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <133000000>; 174 clock-output-names = "clk_ext2"; 175 }; 176 177 clk_ext3: clock-ext3 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext3"; 182 }; 183 184 clk_ext4: clock-ext4 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency= <133000000>; 188 clock-output-names = "clk_ext4"; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 pmu { 197 compatible = "arm,armv8-pmuv3"; 198 interrupts = <GIC_PPI 7 199 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 200 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 209 clock-frequency = <8000000>; 210 arm,no-tick-in-suspend; 211 }; 212 213 thermal-zones { 214 cpu-thermal { 215 polling-delay-passive = <250>; 216 polling-delay = <2000>; 217 thermal-sensors = <&tmu>; 218 trips { 219 cpu_alert0: trip0 { 220 temperature = <85000>; 221 hysteresis = <2000>; 222 type = "passive"; 223 }; 224 225 cpu_crit0: trip1 { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 232 cooling-maps { 233 map0 { 234 trip = <&cpu_alert0>; 235 cooling-device = 236 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 237 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 238 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 239 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 240 }; 241 }; 242 }; 243 }; 244 245 usbphynop1: usbphynop1 { 246 #phy-cells = <0>; 247 compatible = "usb-nop-xceiv"; 248 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 249 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 250 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 251 clock-names = "main_clk"; 252 }; 253 254 usbphynop2: usbphynop2 { 255 #phy-cells = <0>; 256 compatible = "usb-nop-xceiv"; 257 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 258 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 259 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 260 clock-names = "main_clk"; 261 }; 262 263 soc@0 { 264 compatible = "simple-bus"; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges = <0x0 0x0 0x0 0x3e000000>; 268 269 aips1: bus@30000000 { 270 compatible = "fsl,aips-bus", "simple-bus"; 271 reg = <0x30000000 0x400000>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0x30000000 0x30000000 0x400000>; 275 276 sai1: sai@30010000 { 277 #sound-dai-cells = <0>; 278 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 279 reg = <0x30010000 0x10000>; 280 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 282 <&clk IMX8MM_CLK_SAI1_ROOT>, 283 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 284 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 285 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 286 dma-names = "rx", "tx"; 287 status = "disabled"; 288 }; 289 290 sai2: sai@30020000 { 291 #sound-dai-cells = <0>; 292 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 293 reg = <0x30020000 0x10000>; 294 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 296 <&clk IMX8MM_CLK_SAI2_ROOT>, 297 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 298 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 299 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 300 dma-names = "rx", "tx"; 301 status = "disabled"; 302 }; 303 304 sai3: sai@30030000 { 305 #sound-dai-cells = <0>; 306 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 307 reg = <0x30030000 0x10000>; 308 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 310 <&clk IMX8MM_CLK_SAI3_ROOT>, 311 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 312 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 313 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 314 dma-names = "rx", "tx"; 315 status = "disabled"; 316 }; 317 318 sai5: sai@30050000 { 319 #sound-dai-cells = <0>; 320 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 321 reg = <0x30050000 0x10000>; 322 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 324 <&clk IMX8MM_CLK_SAI5_ROOT>, 325 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 326 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 327 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 328 dma-names = "rx", "tx"; 329 status = "disabled"; 330 }; 331 332 sai6: sai@30060000 { 333 #sound-dai-cells = <0>; 334 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 335 reg = <0x30060000 0x10000>; 336 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 338 <&clk IMX8MM_CLK_SAI6_ROOT>, 339 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 340 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 341 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 342 dma-names = "rx", "tx"; 343 status = "disabled"; 344 }; 345 346 micfil: audio-controller@30080000 { 347 compatible = "fsl,imx8mm-micfil"; 348 reg = <0x30080000 0x10000>; 349 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 354 <&clk IMX8MM_CLK_PDM_ROOT>, 355 <&clk IMX8MM_AUDIO_PLL1_OUT>, 356 <&clk IMX8MM_AUDIO_PLL2_OUT>, 357 <&clk IMX8MM_CLK_EXT3>; 358 clock-names = "ipg_clk", "ipg_clk_app", 359 "pll8k", "pll11k", "clkext3"; 360 dmas = <&sdma2 24 25 0x80000000>; 361 dma-names = "rx"; 362 status = "disabled"; 363 }; 364 365 spdif1: spdif@30090000 { 366 compatible = "fsl,imx35-spdif"; 367 reg = <0x30090000 0x10000>; 368 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 370 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 371 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 372 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 373 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 374 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 375 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 376 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 377 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 378 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 379 clock-names = "core", "rxtx0", 380 "rxtx1", "rxtx2", 381 "rxtx3", "rxtx4", 382 "rxtx5", "rxtx6", 383 "rxtx7", "spba"; 384 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 385 dma-names = "rx", "tx"; 386 status = "disabled"; 387 }; 388 389 gpio1: gpio@30200000 { 390 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 391 reg = <0x30200000 0x10000>; 392 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 395 gpio-controller; 396 #gpio-cells = <2>; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 gpio-ranges = <&iomuxc 0 10 30>; 400 }; 401 402 gpio2: gpio@30210000 { 403 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 404 reg = <0x30210000 0x10000>; 405 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 gpio-ranges = <&iomuxc 0 40 21>; 413 }; 414 415 gpio3: gpio@30220000 { 416 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 417 reg = <0x30220000 0x10000>; 418 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 gpio-ranges = <&iomuxc 0 61 26>; 426 }; 427 428 gpio4: gpio@30230000 { 429 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 430 reg = <0x30230000 0x10000>; 431 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 434 gpio-controller; 435 #gpio-cells = <2>; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 gpio-ranges = <&iomuxc 0 87 32>; 439 }; 440 441 gpio5: gpio@30240000 { 442 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 443 reg = <0x30240000 0x10000>; 444 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 gpio-ranges = <&iomuxc 0 119 30>; 452 }; 453 454 tmu: tmu@30260000 { 455 compatible = "fsl,imx8mm-tmu"; 456 reg = <0x30260000 0x10000>; 457 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 458 #thermal-sensor-cells = <0>; 459 }; 460 461 wdog1: watchdog@30280000 { 462 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 463 reg = <0x30280000 0x10000>; 464 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 466 status = "disabled"; 467 }; 468 469 wdog2: watchdog@30290000 { 470 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 471 reg = <0x30290000 0x10000>; 472 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 474 status = "disabled"; 475 }; 476 477 wdog3: watchdog@302a0000 { 478 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 479 reg = <0x302a0000 0x10000>; 480 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 482 status = "disabled"; 483 }; 484 485 sdma2: dma-controller@302c0000 { 486 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 487 reg = <0x302c0000 0x10000>; 488 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 490 <&clk IMX8MM_CLK_SDMA2_ROOT>; 491 clock-names = "ipg", "ahb"; 492 #dma-cells = <3>; 493 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 494 }; 495 496 sdma3: dma-controller@302b0000 { 497 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 498 reg = <0x302b0000 0x10000>; 499 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 501 <&clk IMX8MM_CLK_SDMA3_ROOT>; 502 clock-names = "ipg", "ahb"; 503 #dma-cells = <3>; 504 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 505 }; 506 507 iomuxc: pinctrl@30330000 { 508 compatible = "fsl,imx8mm-iomuxc"; 509 reg = <0x30330000 0x10000>; 510 }; 511 512 gpr: iomuxc-gpr@30340000 { 513 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 514 reg = <0x30340000 0x10000>; 515 }; 516 517 ocotp: efuse@30350000 { 518 compatible = "fsl,imx8mm-ocotp", "syscon"; 519 reg = <0x30350000 0x10000>; 520 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 521 /* For nvmem subnodes */ 522 #address-cells = <1>; 523 #size-cells = <1>; 524 525 cpu_speed_grade: speed-grade@10 { 526 reg = <0x10 4>; 527 }; 528 }; 529 530 anatop: anatop@30360000 { 531 compatible = "fsl,imx8mm-anatop", "syscon"; 532 reg = <0x30360000 0x10000>; 533 }; 534 535 snvs: snvs@30370000 { 536 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 537 reg = <0x30370000 0x10000>; 538 539 snvs_rtc: snvs-rtc-lp { 540 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 541 regmap = <&snvs>; 542 offset = <0x34>; 543 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 546 clock-names = "snvs-rtc"; 547 }; 548 549 snvs_pwrkey: snvs-powerkey { 550 compatible = "fsl,sec-v4.0-pwrkey"; 551 regmap = <&snvs>; 552 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 554 clock-names = "snvs-pwrkey"; 555 linux,keycode = <KEY_POWER>; 556 wakeup-source; 557 status = "disabled"; 558 }; 559 }; 560 561 clk: clock-controller@30380000 { 562 compatible = "fsl,imx8mm-ccm"; 563 reg = <0x30380000 0x10000>; 564 #clock-cells = <1>; 565 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 566 <&clk_ext3>, <&clk_ext4>; 567 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 568 "clk_ext3", "clk_ext4"; 569 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 570 <&clk IMX8MM_CLK_A53_CORE>, 571 <&clk IMX8MM_CLK_NOC>, 572 <&clk IMX8MM_CLK_AUDIO_AHB>, 573 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 574 <&clk IMX8MM_SYS_PLL3>, 575 <&clk IMX8MM_VIDEO_PLL1>, 576 <&clk IMX8MM_AUDIO_PLL1>, 577 <&clk IMX8MM_AUDIO_PLL2>; 578 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 579 <&clk IMX8MM_ARM_PLL_OUT>, 580 <&clk IMX8MM_SYS_PLL3_OUT>, 581 <&clk IMX8MM_SYS_PLL1_800M>; 582 assigned-clock-rates = <0>, <0>, <0>, 583 <400000000>, 584 <400000000>, 585 <750000000>, 586 <594000000>, 587 <393216000>, 588 <361267200>; 589 }; 590 591 src: reset-controller@30390000 { 592 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 593 reg = <0x30390000 0x10000>; 594 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 595 #reset-cells = <1>; 596 }; 597 598 gpc: gpc@303a0000 { 599 compatible = "fsl,imx8mm-gpc"; 600 reg = <0x303a0000 0x10000>; 601 interrupt-parent = <&gic>; 602 interrupt-controller; 603 #interrupt-cells = <3>; 604 605 pgc { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 609 pgc_hsiomix: power-domain@0 { 610 #power-domain-cells = <0>; 611 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; 612 clocks = <&clk IMX8MM_CLK_USB_BUS>; 613 }; 614 615 pgc_pcie: power-domain@1 { 616 #power-domain-cells = <0>; 617 reg = <IMX8MM_POWER_DOMAIN_PCIE>; 618 power-domains = <&pgc_hsiomix>; 619 }; 620 621 pgc_otg1: power-domain@2 { 622 #power-domain-cells = <0>; 623 reg = <IMX8MM_POWER_DOMAIN_OTG1>; 624 power-domains = <&pgc_hsiomix>; 625 }; 626 627 pgc_otg2: power-domain@3 { 628 #power-domain-cells = <0>; 629 reg = <IMX8MM_POWER_DOMAIN_OTG2>; 630 power-domains = <&pgc_hsiomix>; 631 }; 632 633 pgc_gpumix: power-domain@4 { 634 #power-domain-cells = <0>; 635 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; 636 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 637 <&clk IMX8MM_CLK_GPU_AHB>; 638 }; 639 640 pgc_gpu: power-domain@5 { 641 #power-domain-cells = <0>; 642 reg = <IMX8MM_POWER_DOMAIN_GPU>; 643 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 644 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 645 <&clk IMX8MM_CLK_GPU2D_ROOT>, 646 <&clk IMX8MM_CLK_GPU3D_ROOT>; 647 resets = <&src IMX8MQ_RESET_GPU_RESET>; 648 power-domains = <&pgc_gpumix>; 649 }; 650 651 dispmix_pd: power-domain@10 { 652 #power-domain-cells = <0>; 653 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>; 654 clocks = <&clk IMX8MM_CLK_DISP_ROOT>, 655 <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 656 <&clk IMX8MM_CLK_DISP_APB_ROOT>; 657 }; 658 659 mipi_pd: power-domain@11 { 660 #power-domain-cells = <0>; 661 reg = <IMX8MM_POWER_DOMAIN_MIPI>; 662 power-domains = <&dispmix_pd>; 663 }; 664 }; 665 }; 666 }; 667 668 aips2: bus@30400000 { 669 compatible = "fsl,aips-bus", "simple-bus"; 670 reg = <0x30400000 0x400000>; 671 #address-cells = <1>; 672 #size-cells = <1>; 673 ranges = <0x30400000 0x30400000 0x400000>; 674 675 pwm1: pwm@30660000 { 676 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 677 reg = <0x30660000 0x10000>; 678 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 680 <&clk IMX8MM_CLK_PWM1_ROOT>; 681 clock-names = "ipg", "per"; 682 #pwm-cells = <2>; 683 status = "disabled"; 684 }; 685 686 pwm2: pwm@30670000 { 687 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 688 reg = <0x30670000 0x10000>; 689 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 691 <&clk IMX8MM_CLK_PWM2_ROOT>; 692 clock-names = "ipg", "per"; 693 #pwm-cells = <2>; 694 status = "disabled"; 695 }; 696 697 pwm3: pwm@30680000 { 698 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 699 reg = <0x30680000 0x10000>; 700 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 702 <&clk IMX8MM_CLK_PWM3_ROOT>; 703 clock-names = "ipg", "per"; 704 #pwm-cells = <2>; 705 status = "disabled"; 706 }; 707 708 pwm4: pwm@30690000 { 709 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 710 reg = <0x30690000 0x10000>; 711 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 713 <&clk IMX8MM_CLK_PWM4_ROOT>; 714 clock-names = "ipg", "per"; 715 #pwm-cells = <2>; 716 status = "disabled"; 717 }; 718 719 system_counter: timer@306a0000 { 720 compatible = "nxp,sysctr-timer"; 721 reg = <0x306a0000 0x20000>; 722 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&osc_24m>; 724 clock-names = "per"; 725 }; 726 }; 727 728 aips3: bus@30800000 { 729 compatible = "fsl,aips-bus", "simple-bus"; 730 reg = <0x30800000 0x400000>; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 ranges = <0x30800000 0x30800000 0x400000>, 734 <0x8000000 0x8000000 0x10000000>; 735 736 ecspi1: spi@30820000 { 737 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 reg = <0x30820000 0x10000>; 741 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 743 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 744 clock-names = "ipg", "per"; 745 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 746 dma-names = "rx", "tx"; 747 status = "disabled"; 748 }; 749 750 ecspi2: spi@30830000 { 751 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 reg = <0x30830000 0x10000>; 755 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 757 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 758 clock-names = "ipg", "per"; 759 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 760 dma-names = "rx", "tx"; 761 status = "disabled"; 762 }; 763 764 ecspi3: spi@30840000 { 765 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 reg = <0x30840000 0x10000>; 769 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 771 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 772 clock-names = "ipg", "per"; 773 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 774 dma-names = "rx", "tx"; 775 status = "disabled"; 776 }; 777 778 uart1: serial@30860000 { 779 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 780 reg = <0x30860000 0x10000>; 781 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 783 <&clk IMX8MM_CLK_UART1_ROOT>; 784 clock-names = "ipg", "per"; 785 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 786 dma-names = "rx", "tx"; 787 status = "disabled"; 788 }; 789 790 uart3: serial@30880000 { 791 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 792 reg = <0x30880000 0x10000>; 793 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 795 <&clk IMX8MM_CLK_UART3_ROOT>; 796 clock-names = "ipg", "per"; 797 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 798 dma-names = "rx", "tx"; 799 status = "disabled"; 800 }; 801 802 uart2: serial@30890000 { 803 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 804 reg = <0x30890000 0x10000>; 805 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 807 <&clk IMX8MM_CLK_UART2_ROOT>; 808 clock-names = "ipg", "per"; 809 status = "disabled"; 810 }; 811 812 crypto: crypto@30900000 { 813 compatible = "fsl,sec-v4.0"; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 reg = <0x30900000 0x40000>; 817 ranges = <0 0x30900000 0x40000>; 818 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clk IMX8MM_CLK_AHB>, 820 <&clk IMX8MM_CLK_IPG_ROOT>; 821 clock-names = "aclk", "ipg"; 822 823 sec_jr0: jr@1000 { 824 compatible = "fsl,sec-v4.0-job-ring"; 825 reg = <0x1000 0x1000>; 826 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 827 }; 828 829 sec_jr1: jr@2000 { 830 compatible = "fsl,sec-v4.0-job-ring"; 831 reg = <0x2000 0x1000>; 832 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 833 }; 834 835 sec_jr2: jr@3000 { 836 compatible = "fsl,sec-v4.0-job-ring"; 837 reg = <0x3000 0x1000>; 838 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 839 }; 840 }; 841 842 i2c1: i2c@30a20000 { 843 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 reg = <0x30a20000 0x10000>; 847 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 849 status = "disabled"; 850 }; 851 852 i2c2: i2c@30a30000 { 853 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 reg = <0x30a30000 0x10000>; 857 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 859 status = "disabled"; 860 }; 861 862 i2c3: i2c@30a40000 { 863 #address-cells = <1>; 864 #size-cells = <0>; 865 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 866 reg = <0x30a40000 0x10000>; 867 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 869 status = "disabled"; 870 }; 871 872 i2c4: i2c@30a50000 { 873 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 reg = <0x30a50000 0x10000>; 877 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 879 status = "disabled"; 880 }; 881 882 uart4: serial@30a60000 { 883 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 884 reg = <0x30a60000 0x10000>; 885 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 887 <&clk IMX8MM_CLK_UART4_ROOT>; 888 clock-names = "ipg", "per"; 889 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 890 dma-names = "rx", "tx"; 891 status = "disabled"; 892 }; 893 894 mu: mailbox@30aa0000 { 895 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 896 reg = <0x30aa0000 0x10000>; 897 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 899 #mbox-cells = <2>; 900 }; 901 902 usdhc1: mmc@30b40000 { 903 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 904 reg = <0x30b40000 0x10000>; 905 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 907 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 908 <&clk IMX8MM_CLK_USDHC1_ROOT>; 909 clock-names = "ipg", "ahb", "per"; 910 fsl,tuning-start-tap = <20>; 911 fsl,tuning-step= <2>; 912 bus-width = <4>; 913 status = "disabled"; 914 }; 915 916 usdhc2: mmc@30b50000 { 917 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 918 reg = <0x30b50000 0x10000>; 919 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 921 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 922 <&clk IMX8MM_CLK_USDHC2_ROOT>; 923 clock-names = "ipg", "ahb", "per"; 924 fsl,tuning-start-tap = <20>; 925 fsl,tuning-step= <2>; 926 bus-width = <4>; 927 status = "disabled"; 928 }; 929 930 usdhc3: mmc@30b60000 { 931 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 932 reg = <0x30b60000 0x10000>; 933 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 935 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 936 <&clk IMX8MM_CLK_USDHC3_ROOT>; 937 clock-names = "ipg", "ahb", "per"; 938 fsl,tuning-start-tap = <20>; 939 fsl,tuning-step= <2>; 940 bus-width = <4>; 941 status = "disabled"; 942 }; 943 944 flexspi: spi@30bb0000 { 945 #address-cells = <1>; 946 #size-cells = <0>; 947 compatible = "nxp,imx8mm-fspi"; 948 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 949 reg-names = "fspi_base", "fspi_mmap"; 950 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 952 <&clk IMX8MM_CLK_QSPI_ROOT>; 953 clock-names = "fspi", "fspi_en"; 954 status = "disabled"; 955 }; 956 957 sdma1: dma-controller@30bd0000 { 958 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 959 reg = <0x30bd0000 0x10000>; 960 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 962 <&clk IMX8MM_CLK_AHB>; 963 clock-names = "ipg", "ahb"; 964 #dma-cells = <3>; 965 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 966 }; 967 968 fec1: ethernet@30be0000 { 969 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; 970 reg = <0x30be0000 0x10000>; 971 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 976 <&clk IMX8MM_CLK_ENET1_ROOT>, 977 <&clk IMX8MM_CLK_ENET_TIMER>, 978 <&clk IMX8MM_CLK_ENET_REF>, 979 <&clk IMX8MM_CLK_ENET_PHY_REF>; 980 clock-names = "ipg", "ahb", "ptp", 981 "enet_clk_ref", "enet_out"; 982 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 983 <&clk IMX8MM_CLK_ENET_TIMER>, 984 <&clk IMX8MM_CLK_ENET_REF>, 985 <&clk IMX8MM_CLK_ENET_TIMER>; 986 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 987 <&clk IMX8MM_SYS_PLL2_100M>, 988 <&clk IMX8MM_SYS_PLL2_125M>; 989 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 990 fsl,num-tx-queues = <3>; 991 fsl,num-rx-queues = <3>; 992 status = "disabled"; 993 }; 994 995 }; 996 997 aips4: bus@32c00000 { 998 compatible = "fsl,aips-bus", "simple-bus"; 999 reg = <0x32c00000 0x400000>; 1000 #address-cells = <1>; 1001 #size-cells = <1>; 1002 ranges = <0x32c00000 0x32c00000 0x400000>; 1003 1004 usbotg1: usb@32e40000 { 1005 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1006 reg = <0x32e40000 0x200>; 1007 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1009 clock-names = "usb1_ctrl_root_clk"; 1010 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1011 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1012 phys = <&usbphynop1>; 1013 fsl,usbmisc = <&usbmisc1 0>; 1014 power-domains = <&pgc_otg1>; 1015 status = "disabled"; 1016 }; 1017 1018 usbmisc1: usbmisc@32e40200 { 1019 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1020 #index-cells = <1>; 1021 reg = <0x32e40200 0x200>; 1022 }; 1023 1024 usbotg2: usb@32e50000 { 1025 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1026 reg = <0x32e50000 0x200>; 1027 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1029 clock-names = "usb1_ctrl_root_clk"; 1030 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1031 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1032 phys = <&usbphynop2>; 1033 fsl,usbmisc = <&usbmisc2 0>; 1034 power-domains = <&pgc_otg2>; 1035 status = "disabled"; 1036 }; 1037 1038 usbmisc2: usbmisc@32e50200 { 1039 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1040 #index-cells = <1>; 1041 reg = <0x32e50200 0x200>; 1042 }; 1043 1044 }; 1045 1046 dma_apbh: dma-controller@33000000 { 1047 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1048 reg = <0x33000000 0x2000>; 1049 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1053 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1054 #dma-cells = <1>; 1055 dma-channels = <4>; 1056 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1057 }; 1058 1059 gpmi: nand-controller@33002000{ 1060 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1064 reg-names = "gpmi-nand", "bch"; 1065 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1066 interrupt-names = "bch"; 1067 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1068 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1069 clock-names = "gpmi_io", "gpmi_bch_apb"; 1070 dmas = <&dma_apbh 0>; 1071 dma-names = "rx-tx"; 1072 status = "disabled"; 1073 }; 1074 1075 gic: interrupt-controller@38800000 { 1076 compatible = "arm,gic-v3"; 1077 reg = <0x38800000 0x10000>, /* GIC Dist */ 1078 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1079 #interrupt-cells = <3>; 1080 interrupt-controller; 1081 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1082 }; 1083 1084 ddrc: memory-controller@3d400000 { 1085 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1086 reg = <0x3d400000 0x400000>; 1087 clock-names = "core", "pll", "alt", "apb"; 1088 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1089 <&clk IMX8MM_DRAM_PLL>, 1090 <&clk IMX8MM_CLK_DRAM_ALT>, 1091 <&clk IMX8MM_CLK_DRAM_APB>; 1092 }; 1093 1094 ddr-pmu@3d800000 { 1095 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1096 reg = <0x3d800000 0x400000>; 1097 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1098 }; 1099 }; 1100}; 1101