1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7#include <dt-bindings/net/ti-dp83867.h>
8#include "imx8mp.dtsi"
9
10/ {
11	model = "PHYTEC phyCORE-i.MX8MP";
12	compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
13
14	aliases {
15		rtc0 = &rv3028;
16		rtc1 = &snvs_rtc;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x0 0x40000000 0 0x80000000>;
22	};
23};
24
25&A53_0 {
26	cpu-supply = <&buck2>;
27};
28
29&A53_1 {
30	cpu-supply = <&buck2>;
31};
32
33&A53_2 {
34	cpu-supply = <&buck2>;
35};
36
37&A53_3 {
38	cpu-supply = <&buck2>;
39};
40
41/* ethernet 1 */
42&fec {
43	pinctrl-names = "default";
44	pinctrl-0 = <&pinctrl_fec>;
45	phy-mode = "rgmii-id";
46	phy-handle = <&ethphy1>;
47	fsl,magic-packet;
48	status = "okay";
49
50	mdio {
51		#address-cells = <1>;
52		#size-cells = <0>;
53
54		ethphy1: ethernet-phy@0 {
55			compatible = "ethernet-phy-ieee802.3-c22";
56			reg = <0>;
57			interrupt-parent = <&gpio1>;
58			interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
59			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
60			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
61			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
62			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
63			enet-phy-lane-no-swap;
64		};
65	};
66};
67
68&i2c1 {
69	clock-frequency = <400000>;
70	pinctrl-names = "default";
71	pinctrl-0 = <&pinctrl_i2c1>;
72	pinctrl-1 = <&pinctrl_i2c1_gpio>;
73	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
74	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
75	status = "okay";
76
77	pmic: pmic@25 {
78		reg = <0x25>;
79		compatible = "nxp,pca9450c";
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_pmic>;
82		interrupt-parent = <&gpio4>;
83		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
84
85		regulators {
86			buck1: BUCK1 {
87				regulator-compatible = "BUCK1";
88				regulator-min-microvolt = <600000>;
89				regulator-max-microvolt = <2187500>;
90				regulator-boot-on;
91				regulator-always-on;
92				regulator-ramp-delay = <3125>;
93			};
94
95			buck2: BUCK2 {
96				regulator-compatible = "BUCK2";
97				regulator-min-microvolt = <600000>;
98				regulator-max-microvolt = <2187500>;
99				regulator-boot-on;
100				regulator-always-on;
101				regulator-ramp-delay = <3125>;
102			};
103
104			buck4: BUCK4 {
105				regulator-compatible = "BUCK4";
106				regulator-min-microvolt = <600000>;
107				regulator-max-microvolt = <3400000>;
108				regulator-boot-on;
109				regulator-always-on;
110			};
111
112			buck5: BUCK5 {
113				regulator-compatible = "BUCK5";
114				regulator-min-microvolt = <600000>;
115				regulator-max-microvolt = <3400000>;
116				regulator-boot-on;
117				regulator-always-on;
118			};
119
120			buck6: BUCK6 {
121				regulator-compatible = "BUCK6";
122				regulator-min-microvolt = <600000>;
123				regulator-max-microvolt = <3400000>;
124				regulator-boot-on;
125				regulator-always-on;
126			};
127
128			ldo1: LDO1 {
129				regulator-compatible = "LDO1";
130				regulator-min-microvolt = <1600000>;
131				regulator-max-microvolt = <3300000>;
132				regulator-boot-on;
133				regulator-always-on;
134			};
135
136			ldo2: LDO2 {
137				regulator-compatible = "LDO2";
138				regulator-min-microvolt = <800000>;
139				regulator-max-microvolt = <1150000>;
140				regulator-boot-on;
141				regulator-always-on;
142			};
143
144			ldo3: LDO3 {
145				regulator-compatible = "LDO3";
146				regulator-min-microvolt = <800000>;
147				regulator-max-microvolt = <3300000>;
148				regulator-boot-on;
149				regulator-always-on;
150			};
151
152			ldo4: LDO4 {
153				regulator-compatible = "LDO4";
154				regulator-min-microvolt = <800000>;
155				regulator-max-microvolt = <3300000>;
156				regulator-boot-on;
157				regulator-always-on;
158			};
159
160			ldo5: LDO5 {
161				regulator-compatible = "LDO5";
162				regulator-min-microvolt = <1800000>;
163				regulator-max-microvolt = <3300000>;
164			};
165		};
166	};
167
168	eeprom@51 {
169		compatible = "atmel,24c32";
170		reg = <0x51>;
171		pagesize = <32>;
172	};
173
174	rv3028: rtc@52 {
175		compatible = "microcrystal,rv3028";
176		reg = <0x52>;
177		trickle-resistor-ohms = <3000>;
178	};
179};
180
181/* eMMC */
182&usdhc3 {
183	pinctrl-names = "default", "state_100mhz", "state_200mhz";
184	pinctrl-0 = <&pinctrl_usdhc3>;
185	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
186	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
187	bus-width = <8>;
188	non-removable;
189	status = "okay";
190};
191
192&wdog1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_wdog>;
195	fsl,ext-reset-output;
196	status = "okay";
197};
198
199&iomuxc {
200	pinctrl_fec: fecgrp {
201		fsl,pins = <
202			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
203			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
204			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
205			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
206			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
207			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
208			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
209			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
210			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
211			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
212			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
213			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
214			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
215			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
216			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x11
217		>;
218	};
219
220	pinctrl_i2c1: i2c1grp {
221		fsl,pins = <
222			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
223			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
224		>;
225	};
226
227	pinctrl_i2c1_gpio: i2c1gpiogrp {
228		fsl,pins = <
229			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1e3
230			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1e3
231		>;
232	};
233
234	pinctrl_pmic: pmicirqgrp {
235		fsl,pins = <
236			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x141
237		>;
238	};
239
240	pinctrl_usdhc3: usdhc3grp {
241		fsl,pins = <
242			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
243			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
244			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
245			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
246			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
247			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
248			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
249			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
250			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
251			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
252			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
253		>;
254	};
255
256	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
257		fsl,pins = <
258			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
259			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
260			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
261			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
262			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
263			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
264			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
265			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
266			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
267			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
268			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
269		>;
270	};
271
272	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
273		fsl,pins = <
274			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
275			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
276			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
277			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
278			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
279			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
280			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
281			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
282			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
283			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
284			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
285		>;
286	};
287
288	pinctrl_wdog: wdoggrp {
289		fsl,pins = <
290			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
291		>;
292	};
293};
294