1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "imx8mq-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gpc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec1; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 i2c3 = &i2c4; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 ckil: clock-ckil { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <32768>; 48 clock-output-names = "ckil"; 49 }; 50 51 osc_25m: clock-osc-25m { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <25000000>; 55 clock-output-names = "osc_25m"; 56 }; 57 58 osc_27m: clock-osc-27m { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <27000000>; 62 clock-output-names = "osc_27m"; 63 }; 64 65 clk_ext1: clock-ext1 { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <133000000>; 69 clock-output-names = "clk_ext1"; 70 }; 71 72 clk_ext2: clock-ext2 { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <133000000>; 76 clock-output-names = "clk_ext2"; 77 }; 78 79 clk_ext3: clock-ext3 { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <133000000>; 83 clock-output-names = "clk_ext3"; 84 }; 85 86 clk_ext4: clock-ext4 { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency= <133000000>; 90 clock-output-names = "clk_ext4"; 91 }; 92 93 cpus { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 A53_0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0>; 101 clock-latency = <61036>; /* two CLK32 periods */ 102 clocks = <&clk IMX8MQ_CLK_ARM>; 103 enable-method = "psci"; 104 next-level-cache = <&A53_L2>; 105 operating-points-v2 = <&a53_opp_table>; 106 #cooling-cells = <2>; 107 nvmem-cells = <&cpu_speed_grade>; 108 nvmem-cell-names = "speed_grade"; 109 }; 110 111 A53_1: cpu@1 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x1>; 115 clock-latency = <61036>; /* two CLK32 periods */ 116 clocks = <&clk IMX8MQ_CLK_ARM>; 117 enable-method = "psci"; 118 next-level-cache = <&A53_L2>; 119 operating-points-v2 = <&a53_opp_table>; 120 #cooling-cells = <2>; 121 }; 122 123 A53_2: cpu@2 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53"; 126 reg = <0x2>; 127 clock-latency = <61036>; /* two CLK32 periods */ 128 clocks = <&clk IMX8MQ_CLK_ARM>; 129 enable-method = "psci"; 130 next-level-cache = <&A53_L2>; 131 operating-points-v2 = <&a53_opp_table>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_3: cpu@3 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x3>; 139 clock-latency = <61036>; /* two CLK32 periods */ 140 clocks = <&clk IMX8MQ_CLK_ARM>; 141 enable-method = "psci"; 142 next-level-cache = <&A53_L2>; 143 operating-points-v2 = <&a53_opp_table>; 144 #cooling-cells = <2>; 145 }; 146 147 A53_L2: l2-cache0 { 148 compatible = "cache"; 149 }; 150 }; 151 152 a53_opp_table: opp-table { 153 compatible = "operating-points-v2"; 154 opp-shared; 155 156 opp-800000000 { 157 opp-hz = /bits/ 64 <800000000>; 158 opp-microvolt = <900000>; 159 /* Industrial only */ 160 opp-supported-hw = <0xf>, <0x4>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1000000000 { 166 opp-hz = /bits/ 64 <1000000000>; 167 opp-microvolt = <900000>; 168 /* Consumer only */ 169 opp-supported-hw = <0xe>, <0x3>; 170 clock-latency-ns = <150000>; 171 opp-suspend; 172 }; 173 174 opp-1300000000 { 175 opp-hz = /bits/ 64 <1300000000>; 176 opp-microvolt = <1000000>; 177 opp-supported-hw = <0xc>, <0x4>; 178 clock-latency-ns = <150000>; 179 opp-suspend; 180 }; 181 182 opp-1500000000 { 183 opp-hz = /bits/ 64 <1500000000>; 184 opp-microvolt = <1000000>; 185 opp-supported-hw = <0x8>, <0x3>; 186 clock-latency-ns = <150000>; 187 opp-suspend; 188 }; 189 }; 190 191 pmu { 192 compatible = "arm,cortex-a53-pmu"; 193 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-parent = <&gic>; 195 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 196 }; 197 198 psci { 199 compatible = "arm,psci-1.0"; 200 method = "smc"; 201 }; 202 203 thermal-zones { 204 cpu_thermal: cpu-thermal { 205 polling-delay-passive = <250>; 206 polling-delay = <2000>; 207 thermal-sensors = <&tmu 0>; 208 209 trips { 210 cpu_alert: cpu-alert { 211 temperature = <80000>; 212 hysteresis = <2000>; 213 type = "passive"; 214 }; 215 216 cpu-crit { 217 temperature = <90000>; 218 hysteresis = <2000>; 219 type = "critical"; 220 }; 221 }; 222 223 cooling-maps { 224 map0 { 225 trip = <&cpu_alert>; 226 cooling-device = 227 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 228 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 229 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 230 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 231 }; 232 }; 233 }; 234 235 gpu-thermal { 236 polling-delay-passive = <250>; 237 polling-delay = <2000>; 238 thermal-sensors = <&tmu 1>; 239 240 trips { 241 gpu_alert: gpu-alert { 242 temperature = <80000>; 243 hysteresis = <2000>; 244 type = "passive"; 245 }; 246 247 gpu-crit { 248 temperature = <90000>; 249 hysteresis = <2000>; 250 type = "critical"; 251 }; 252 }; 253 254 cooling-maps { 255 map0 { 256 trip = <&gpu_alert>; 257 cooling-device = 258 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 259 }; 260 }; 261 }; 262 263 vpu-thermal { 264 polling-delay-passive = <250>; 265 polling-delay = <2000>; 266 thermal-sensors = <&tmu 2>; 267 268 trips { 269 vpu-crit { 270 temperature = <90000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 }; 276 }; 277 278 timer { 279 compatible = "arm,armv8-timer"; 280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 282 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 283 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 284 interrupt-parent = <&gic>; 285 arm,no-tick-in-suspend; 286 }; 287 288 soc@0 { 289 compatible = "simple-bus"; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges = <0x0 0x0 0x0 0x3e000000>; 293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 294 295 bus@30000000 { /* AIPS1 */ 296 compatible = "fsl,aips-bus", "simple-bus"; 297 reg = <0x30000000 0x400000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges = <0x30000000 0x30000000 0x400000>; 301 302 sai1: sai@30010000 { 303 #sound-dai-cells = <0>; 304 compatible = "fsl,imx8mq-sai"; 305 reg = <0x30010000 0x10000>; 306 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 308 <&clk IMX8MQ_CLK_SAI1_ROOT>, 309 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 310 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 311 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 312 dma-names = "rx", "tx"; 313 status = "disabled"; 314 }; 315 316 sai6: sai@30030000 { 317 #sound-dai-cells = <0>; 318 compatible = "fsl,imx8mq-sai"; 319 reg = <0x30030000 0x10000>; 320 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 322 <&clk IMX8MQ_CLK_SAI6_ROOT>, 323 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 324 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 325 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 sai5: sai@30040000 { 331 #sound-dai-cells = <0>; 332 compatible = "fsl,imx8mq-sai"; 333 reg = <0x30040000 0x10000>; 334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 336 <&clk IMX8MQ_CLK_SAI5_ROOT>, 337 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 338 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 339 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 340 dma-names = "rx", "tx"; 341 status = "disabled"; 342 }; 343 344 sai4: sai@30050000 { 345 #sound-dai-cells = <0>; 346 compatible = "fsl,imx8mq-sai"; 347 reg = <0x30050000 0x10000>; 348 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 350 <&clk IMX8MQ_CLK_SAI4_ROOT>, 351 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 352 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 353 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 354 dma-names = "rx", "tx"; 355 status = "disabled"; 356 }; 357 358 gpio1: gpio@30200000 { 359 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 360 reg = <0x30200000 0x10000>; 361 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 gpio-ranges = <&iomuxc 0 10 30>; 369 }; 370 371 gpio2: gpio@30210000 { 372 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 373 reg = <0x30210000 0x10000>; 374 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 377 gpio-controller; 378 #gpio-cells = <2>; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 gpio-ranges = <&iomuxc 0 40 21>; 382 }; 383 384 gpio3: gpio@30220000 { 385 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 386 reg = <0x30220000 0x10000>; 387 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 gpio-ranges = <&iomuxc 0 61 26>; 395 }; 396 397 gpio4: gpio@30230000 { 398 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 399 reg = <0x30230000 0x10000>; 400 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 gpio-ranges = <&iomuxc 0 87 32>; 408 }; 409 410 gpio5: gpio@30240000 { 411 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 412 reg = <0x30240000 0x10000>; 413 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 gpio-ranges = <&iomuxc 0 119 30>; 421 }; 422 423 tmu: tmu@30260000 { 424 compatible = "fsl,imx8mq-tmu"; 425 reg = <0x30260000 0x10000>; 426 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 428 little-endian; 429 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 430 fsl,tmu-calibration = <0x00000000 0x00000023 431 0x00000001 0x00000029 432 0x00000002 0x0000002f 433 0x00000003 0x00000035 434 0x00000004 0x0000003d 435 0x00000005 0x00000043 436 0x00000006 0x0000004b 437 0x00000007 0x00000051 438 0x00000008 0x00000057 439 0x00000009 0x0000005f 440 0x0000000a 0x00000067 441 0x0000000b 0x0000006f 442 443 0x00010000 0x0000001b 444 0x00010001 0x00000023 445 0x00010002 0x0000002b 446 0x00010003 0x00000033 447 0x00010004 0x0000003b 448 0x00010005 0x00000043 449 0x00010006 0x0000004b 450 0x00010007 0x00000055 451 0x00010008 0x0000005d 452 0x00010009 0x00000067 453 0x0001000a 0x00000070 454 455 0x00020000 0x00000017 456 0x00020001 0x00000023 457 0x00020002 0x0000002d 458 0x00020003 0x00000037 459 0x00020004 0x00000041 460 0x00020005 0x0000004b 461 0x00020006 0x00000057 462 0x00020007 0x00000063 463 0x00020008 0x0000006f 464 465 0x00030000 0x00000015 466 0x00030001 0x00000021 467 0x00030002 0x0000002d 468 0x00030003 0x00000039 469 0x00030004 0x00000045 470 0x00030005 0x00000053 471 0x00030006 0x0000005f 472 0x00030007 0x00000071>; 473 #thermal-sensor-cells = <1>; 474 }; 475 476 wdog1: watchdog@30280000 { 477 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 478 reg = <0x30280000 0x10000>; 479 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 481 status = "disabled"; 482 }; 483 484 wdog2: watchdog@30290000 { 485 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 486 reg = <0x30290000 0x10000>; 487 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 489 status = "disabled"; 490 }; 491 492 wdog3: watchdog@302a0000 { 493 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 494 reg = <0x302a0000 0x10000>; 495 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 497 status = "disabled"; 498 }; 499 500 sdma2: sdma@302c0000 { 501 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 502 reg = <0x302c0000 0x10000>; 503 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 505 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 506 clock-names = "ipg", "ahb"; 507 #dma-cells = <3>; 508 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 509 }; 510 511 lcdif: lcd-controller@30320000 { 512 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 513 reg = <0x30320000 0x10000>; 514 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 516 clock-names = "pix"; 517 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 518 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 519 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 520 <&clk IMX8MQ_VIDEO_PLL1>; 521 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 522 <&clk IMX8MQ_VIDEO_PLL1>, 523 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 524 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 525 status = "disabled"; 526 527 port@0 { 528 lcdif_mipi_dsi: endpoint { 529 remote-endpoint = <&mipi_dsi_lcdif_in>; 530 }; 531 }; 532 }; 533 534 iomuxc: pinctrl@30330000 { 535 compatible = "fsl,imx8mq-iomuxc"; 536 reg = <0x30330000 0x10000>; 537 }; 538 539 iomuxc_gpr: syscon@30340000 { 540 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 541 "syscon", "simple-mfd"; 542 reg = <0x30340000 0x10000>; 543 544 mux: mux-controller { 545 compatible = "mmio-mux"; 546 #mux-control-cells = <1>; 547 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 548 }; 549 }; 550 551 ocotp: efuse@30350000 { 552 compatible = "fsl,imx8mq-ocotp", "syscon"; 553 reg = <0x30350000 0x10000>; 554 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 558 cpu_speed_grade: speed-grade@10 { 559 reg = <0x10 4>; 560 }; 561 }; 562 563 anatop: syscon@30360000 { 564 compatible = "fsl,imx8mq-anatop", "syscon"; 565 reg = <0x30360000 0x10000>; 566 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 567 }; 568 569 snvs: snvs@30370000 { 570 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 571 reg = <0x30370000 0x10000>; 572 573 snvs_rtc: snvs-rtc-lp{ 574 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 575 regmap =<&snvs>; 576 offset = <0x34>; 577 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 580 clock-names = "snvs-rtc"; 581 }; 582 583 snvs_pwrkey: snvs-powerkey { 584 compatible = "fsl,sec-v4.0-pwrkey"; 585 regmap = <&snvs>; 586 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 588 clock-names = "snvs-pwrkey"; 589 linux,keycode = <KEY_POWER>; 590 wakeup-source; 591 status = "disabled"; 592 }; 593 }; 594 595 clk: clock-controller@30380000 { 596 compatible = "fsl,imx8mq-ccm"; 597 reg = <0x30380000 0x10000>; 598 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 600 #clock-cells = <1>; 601 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 602 <&clk_ext1>, <&clk_ext2>, 603 <&clk_ext3>, <&clk_ext4>; 604 clock-names = "ckil", "osc_25m", "osc_27m", 605 "clk_ext1", "clk_ext2", 606 "clk_ext3", "clk_ext4"; 607 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 608 <&clk IMX8MQ_CLK_A53_CORE>, 609 <&clk IMX8MQ_CLK_NOC>, 610 <&clk IMX8MQ_CLK_AUDIO_AHB>, 611 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 612 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 613 <&clk IMX8MQ_AUDIO_PLL1>, 614 <&clk IMX8MQ_AUDIO_PLL2>; 615 assigned-clock-rates = <0>, <0>, 616 <800000000>, 617 <0>, 618 <0>, 619 <0>, 620 <786432000>, 621 <722534400>; 622 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 623 <&clk IMX8MQ_ARM_PLL_OUT>, 624 <0>, 625 <&clk IMX8MQ_SYS2_PLL_500M>, 626 <&clk IMX8MQ_AUDIO_PLL1>, 627 <&clk IMX8MQ_AUDIO_PLL2>; 628 }; 629 630 src: reset-controller@30390000 { 631 compatible = "fsl,imx8mq-src", "syscon"; 632 reg = <0x30390000 0x10000>; 633 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 634 #reset-cells = <1>; 635 }; 636 637 gpc: gpc@303a0000 { 638 compatible = "fsl,imx8mq-gpc"; 639 reg = <0x303a0000 0x10000>; 640 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 641 interrupt-parent = <&gic>; 642 interrupt-controller; 643 #interrupt-cells = <3>; 644 645 pgc { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 649 pgc_mipi: power-domain@0 { 650 #power-domain-cells = <0>; 651 reg = <IMX8M_POWER_DOMAIN_MIPI>; 652 }; 653 654 /* 655 * As per comment in ATF source code: 656 * 657 * PCIE1 and PCIE2 share the 658 * same reset signal, if we 659 * power down PCIE2, PCIE1 660 * will be held in reset too. 661 * 662 * So instead of creating two 663 * separate power domains for 664 * PCIE1 and PCIE2 we create a 665 * link between both and use 666 * it as a shared PCIE power 667 * domain. 668 */ 669 pgc_pcie: power-domain@1 { 670 #power-domain-cells = <0>; 671 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 672 power-domains = <&pgc_pcie2>; 673 }; 674 675 pgc_otg1: power-domain@2 { 676 #power-domain-cells = <0>; 677 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 678 }; 679 680 pgc_otg2: power-domain@3 { 681 #power-domain-cells = <0>; 682 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 683 }; 684 685 pgc_ddr1: power-domain@4 { 686 #power-domain-cells = <0>; 687 reg = <IMX8M_POWER_DOMAIN_DDR1>; 688 }; 689 690 pgc_gpu: power-domain@5 { 691 #power-domain-cells = <0>; 692 reg = <IMX8M_POWER_DOMAIN_GPU>; 693 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 694 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 695 <&clk IMX8MQ_CLK_GPU_AXI>, 696 <&clk IMX8MQ_CLK_GPU_AHB>; 697 }; 698 699 pgc_vpu: power-domain@6 { 700 #power-domain-cells = <0>; 701 reg = <IMX8M_POWER_DOMAIN_VPU>; 702 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; 703 }; 704 705 pgc_disp: power-domain@7 { 706 #power-domain-cells = <0>; 707 reg = <IMX8M_POWER_DOMAIN_DISP>; 708 }; 709 710 pgc_mipi_csi1: power-domain@8 { 711 #power-domain-cells = <0>; 712 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 713 }; 714 715 pgc_mipi_csi2: power-domain@9 { 716 #power-domain-cells = <0>; 717 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 718 }; 719 720 pgc_pcie2: power-domain@a { 721 #power-domain-cells = <0>; 722 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 723 }; 724 }; 725 }; 726 }; 727 728 bus@30400000 { /* AIPS2 */ 729 compatible = "fsl,aips-bus", "simple-bus"; 730 reg = <0x30400000 0x400000>; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 ranges = <0x30400000 0x30400000 0x400000>; 734 735 pwm1: pwm@30660000 { 736 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 737 reg = <0x30660000 0x10000>; 738 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 740 <&clk IMX8MQ_CLK_PWM1_ROOT>; 741 clock-names = "ipg", "per"; 742 #pwm-cells = <2>; 743 status = "disabled"; 744 }; 745 746 pwm2: pwm@30670000 { 747 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 748 reg = <0x30670000 0x10000>; 749 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 751 <&clk IMX8MQ_CLK_PWM2_ROOT>; 752 clock-names = "ipg", "per"; 753 #pwm-cells = <2>; 754 status = "disabled"; 755 }; 756 757 pwm3: pwm@30680000 { 758 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 759 reg = <0x30680000 0x10000>; 760 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 762 <&clk IMX8MQ_CLK_PWM3_ROOT>; 763 clock-names = "ipg", "per"; 764 #pwm-cells = <2>; 765 status = "disabled"; 766 }; 767 768 pwm4: pwm@30690000 { 769 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 770 reg = <0x30690000 0x10000>; 771 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 773 <&clk IMX8MQ_CLK_PWM4_ROOT>; 774 clock-names = "ipg", "per"; 775 #pwm-cells = <2>; 776 status = "disabled"; 777 }; 778 779 system_counter: timer@306a0000 { 780 compatible = "nxp,sysctr-timer"; 781 reg = <0x306a0000 0x20000>; 782 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&osc_25m>; 784 clock-names = "per"; 785 }; 786 }; 787 788 bus@30800000 { /* AIPS3 */ 789 compatible = "fsl,aips-bus", "simple-bus"; 790 reg = <0x30800000 0x400000>; 791 #address-cells = <1>; 792 #size-cells = <1>; 793 ranges = <0x30800000 0x30800000 0x400000>, 794 <0x08000000 0x08000000 0x10000000>; 795 796 spdif1: spdif@30810000 { 797 compatible = "fsl,imx35-spdif"; 798 reg = <0x30810000 0x10000>; 799 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 801 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 802 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 803 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 804 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 805 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 806 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 807 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 808 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 809 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 810 clock-names = "core", "rxtx0", 811 "rxtx1", "rxtx2", 812 "rxtx3", "rxtx4", 813 "rxtx5", "rxtx6", 814 "rxtx7", "spba"; 815 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 816 dma-names = "rx", "tx"; 817 status = "disabled"; 818 }; 819 820 ecspi1: spi@30820000 { 821 #address-cells = <1>; 822 #size-cells = <0>; 823 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 824 reg = <0x30820000 0x10000>; 825 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 827 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 828 clock-names = "ipg", "per"; 829 status = "disabled"; 830 }; 831 832 ecspi2: spi@30830000 { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 836 reg = <0x30830000 0x10000>; 837 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 839 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 840 clock-names = "ipg", "per"; 841 status = "disabled"; 842 }; 843 844 ecspi3: spi@30840000 { 845 #address-cells = <1>; 846 #size-cells = <0>; 847 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 848 reg = <0x30840000 0x10000>; 849 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 851 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 852 clock-names = "ipg", "per"; 853 status = "disabled"; 854 }; 855 856 uart1: serial@30860000 { 857 compatible = "fsl,imx8mq-uart", 858 "fsl,imx6q-uart"; 859 reg = <0x30860000 0x10000>; 860 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 862 <&clk IMX8MQ_CLK_UART1_ROOT>; 863 clock-names = "ipg", "per"; 864 status = "disabled"; 865 }; 866 867 uart3: serial@30880000 { 868 compatible = "fsl,imx8mq-uart", 869 "fsl,imx6q-uart"; 870 reg = <0x30880000 0x10000>; 871 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 873 <&clk IMX8MQ_CLK_UART3_ROOT>; 874 clock-names = "ipg", "per"; 875 status = "disabled"; 876 }; 877 878 uart2: serial@30890000 { 879 compatible = "fsl,imx8mq-uart", 880 "fsl,imx6q-uart"; 881 reg = <0x30890000 0x10000>; 882 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 884 <&clk IMX8MQ_CLK_UART2_ROOT>; 885 clock-names = "ipg", "per"; 886 status = "disabled"; 887 }; 888 889 spdif2: spdif@308a0000 { 890 compatible = "fsl,imx35-spdif"; 891 reg = <0x308a0000 0x10000>; 892 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 894 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 895 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 896 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 897 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 898 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 899 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 900 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 901 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 902 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 903 clock-names = "core", "rxtx0", 904 "rxtx1", "rxtx2", 905 "rxtx3", "rxtx4", 906 "rxtx5", "rxtx6", 907 "rxtx7", "spba"; 908 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 909 dma-names = "rx", "tx"; 910 status = "disabled"; 911 }; 912 913 sai2: sai@308b0000 { 914 #sound-dai-cells = <0>; 915 compatible = "fsl,imx8mq-sai"; 916 reg = <0x308b0000 0x10000>; 917 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 919 <&clk IMX8MQ_CLK_SAI2_ROOT>, 920 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 921 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 922 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 923 dma-names = "rx", "tx"; 924 status = "disabled"; 925 }; 926 927 sai3: sai@308c0000 { 928 #sound-dai-cells = <0>; 929 compatible = "fsl,imx8mq-sai"; 930 reg = <0x308c0000 0x10000>; 931 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 933 <&clk IMX8MQ_CLK_SAI3_ROOT>, 934 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 935 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 936 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 937 dma-names = "rx", "tx"; 938 status = "disabled"; 939 }; 940 941 crypto: crypto@30900000 { 942 compatible = "fsl,sec-v4.0"; 943 #address-cells = <1>; 944 #size-cells = <1>; 945 reg = <0x30900000 0x40000>; 946 ranges = <0 0x30900000 0x40000>; 947 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clk IMX8MQ_CLK_AHB>, 949 <&clk IMX8MQ_CLK_IPG_ROOT>; 950 clock-names = "aclk", "ipg"; 951 952 sec_jr0: jr@1000 { 953 compatible = "fsl,sec-v4.0-job-ring"; 954 reg = <0x1000 0x1000>; 955 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 956 }; 957 958 sec_jr1: jr@2000 { 959 compatible = "fsl,sec-v4.0-job-ring"; 960 reg = <0x2000 0x1000>; 961 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 962 }; 963 964 sec_jr2: jr@3000 { 965 compatible = "fsl,sec-v4.0-job-ring"; 966 reg = <0x3000 0x1000>; 967 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 968 }; 969 }; 970 971 mipi_dsi: mipi-dsi@30a00000 { 972 compatible = "fsl,imx8mq-nwl-dsi"; 973 reg = <0x30a00000 0x300>; 974 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 975 <&clk IMX8MQ_CLK_DSI_AHB>, 976 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 977 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 978 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 979 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 980 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 981 <&clk IMX8MQ_CLK_DSI_CORE>, 982 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 983 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 984 <&clk IMX8MQ_SYS1_PLL_266M>; 985 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 986 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 987 mux-controls = <&mux 0>; 988 power-domains = <&pgc_mipi>; 989 phys = <&dphy>; 990 phy-names = "dphy"; 991 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 992 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 993 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 994 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 995 reset-names = "byte", "dpi", "esc", "pclk"; 996 status = "disabled"; 997 998 ports { 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 port@0 { 1003 reg = <0>; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 mipi_dsi_lcdif_in: endpoint@0 { 1007 reg = <0>; 1008 remote-endpoint = <&lcdif_mipi_dsi>; 1009 }; 1010 }; 1011 }; 1012 }; 1013 1014 dphy: dphy@30a00300 { 1015 compatible = "fsl,imx8mq-mipi-dphy"; 1016 reg = <0x30a00300 0x100>; 1017 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1018 clock-names = "phy_ref"; 1019 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1020 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1021 assigned-clock-rates = <24000000>; 1022 #phy-cells = <0>; 1023 power-domains = <&pgc_mipi>; 1024 status = "disabled"; 1025 }; 1026 1027 i2c1: i2c@30a20000 { 1028 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1029 reg = <0x30a20000 0x10000>; 1030 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c2: i2c@30a30000 { 1038 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1039 reg = <0x30a30000 0x10000>; 1040 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c3: i2c@30a40000 { 1048 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1049 reg = <0x30a40000 0x10000>; 1050 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 status = "disabled"; 1055 }; 1056 1057 i2c4: i2c@30a50000 { 1058 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1059 reg = <0x30a50000 0x10000>; 1060 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 uart4: serial@30a60000 { 1068 compatible = "fsl,imx8mq-uart", 1069 "fsl,imx6q-uart"; 1070 reg = <0x30a60000 0x10000>; 1071 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1073 <&clk IMX8MQ_CLK_UART4_ROOT>; 1074 clock-names = "ipg", "per"; 1075 status = "disabled"; 1076 }; 1077 1078 mu: mailbox@30aa0000 { 1079 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1080 reg = <0x30aa0000 0x10000>; 1081 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1083 #mbox-cells = <2>; 1084 }; 1085 1086 usdhc1: mmc@30b40000 { 1087 compatible = "fsl,imx8mq-usdhc", 1088 "fsl,imx7d-usdhc"; 1089 reg = <0x30b40000 0x10000>; 1090 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1092 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1093 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1094 clock-names = "ipg", "ahb", "per"; 1095 fsl,tuning-start-tap = <20>; 1096 fsl,tuning-step = <2>; 1097 bus-width = <4>; 1098 status = "disabled"; 1099 }; 1100 1101 usdhc2: mmc@30b50000 { 1102 compatible = "fsl,imx8mq-usdhc", 1103 "fsl,imx7d-usdhc"; 1104 reg = <0x30b50000 0x10000>; 1105 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1107 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1108 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1109 clock-names = "ipg", "ahb", "per"; 1110 fsl,tuning-start-tap = <20>; 1111 fsl,tuning-step = <2>; 1112 bus-width = <4>; 1113 status = "disabled"; 1114 }; 1115 1116 qspi0: spi@30bb0000 { 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1120 reg = <0x30bb0000 0x10000>, 1121 <0x08000000 0x10000000>; 1122 reg-names = "QuadSPI", "QuadSPI-memory"; 1123 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1125 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1126 clock-names = "qspi_en", "qspi"; 1127 status = "disabled"; 1128 }; 1129 1130 sdma1: sdma@30bd0000 { 1131 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1132 reg = <0x30bd0000 0x10000>; 1133 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1135 <&clk IMX8MQ_CLK_AHB>; 1136 clock-names = "ipg", "ahb"; 1137 #dma-cells = <3>; 1138 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1139 }; 1140 1141 fec1: ethernet@30be0000 { 1142 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1143 reg = <0x30be0000 0x10000>; 1144 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1149 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1150 <&clk IMX8MQ_CLK_ENET_TIMER>, 1151 <&clk IMX8MQ_CLK_ENET_REF>, 1152 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1153 clock-names = "ipg", "ahb", "ptp", 1154 "enet_clk_ref", "enet_out"; 1155 fsl,num-tx-queues = <3>; 1156 fsl,num-rx-queues = <3>; 1157 status = "disabled"; 1158 }; 1159 }; 1160 1161 bus@32c00000 { /* AIPS4 */ 1162 compatible = "fsl,aips-bus", "simple-bus"; 1163 reg = <0x32c00000 0x400000>; 1164 #address-cells = <1>; 1165 #size-cells = <1>; 1166 ranges = <0x32c00000 0x32c00000 0x400000>; 1167 1168 irqsteer: interrupt-controller@32e2d000 { 1169 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1170 reg = <0x32e2d000 0x1000>; 1171 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1173 clock-names = "ipg"; 1174 fsl,channel = <0>; 1175 fsl,num-irqs = <64>; 1176 interrupt-controller; 1177 #interrupt-cells = <1>; 1178 }; 1179 }; 1180 1181 gpu: gpu@38000000 { 1182 compatible = "vivante,gc"; 1183 reg = <0x38000000 0x40000>; 1184 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1186 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1187 <&clk IMX8MQ_CLK_GPU_AXI>, 1188 <&clk IMX8MQ_CLK_GPU_AHB>; 1189 clock-names = "core", "shader", "bus", "reg"; 1190 #cooling-cells = <2>; 1191 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1192 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1193 <&clk IMX8MQ_CLK_GPU_AXI>, 1194 <&clk IMX8MQ_CLK_GPU_AHB>, 1195 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1196 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1197 <&clk IMX8MQ_GPU_PLL_OUT>, 1198 <&clk IMX8MQ_GPU_PLL_OUT>, 1199 <&clk IMX8MQ_GPU_PLL_OUT>, 1200 <&clk IMX8MQ_GPU_PLL>; 1201 assigned-clock-rates = <800000000>, <800000000>, 1202 <800000000>, <800000000>, <0>; 1203 power-domains = <&pgc_gpu>; 1204 }; 1205 1206 usb_dwc3_0: usb@38100000 { 1207 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1208 reg = <0x38100000 0x10000>; 1209 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1210 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1211 <&clk IMX8MQ_CLK_32K>; 1212 clock-names = "bus_early", "ref", "suspend"; 1213 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1214 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1215 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1216 <&clk IMX8MQ_SYS1_PLL_100M>; 1217 assigned-clock-rates = <500000000>, <100000000>; 1218 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1219 phys = <&usb3_phy0>, <&usb3_phy0>; 1220 phy-names = "usb2-phy", "usb3-phy"; 1221 power-domains = <&pgc_otg1>; 1222 usb3-resume-missing-cas; 1223 status = "disabled"; 1224 }; 1225 1226 usb3_phy0: usb-phy@381f0040 { 1227 compatible = "fsl,imx8mq-usb-phy"; 1228 reg = <0x381f0040 0x40>; 1229 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1230 clock-names = "phy"; 1231 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1232 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1233 assigned-clock-rates = <100000000>; 1234 #phy-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 usb_dwc3_1: usb@38200000 { 1239 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1240 reg = <0x38200000 0x10000>; 1241 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1242 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1243 <&clk IMX8MQ_CLK_32K>; 1244 clock-names = "bus_early", "ref", "suspend"; 1245 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1246 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1247 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1248 <&clk IMX8MQ_SYS1_PLL_100M>; 1249 assigned-clock-rates = <500000000>, <100000000>; 1250 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1251 phys = <&usb3_phy1>, <&usb3_phy1>; 1252 phy-names = "usb2-phy", "usb3-phy"; 1253 power-domains = <&pgc_otg2>; 1254 usb3-resume-missing-cas; 1255 status = "disabled"; 1256 }; 1257 1258 usb3_phy1: usb-phy@382f0040 { 1259 compatible = "fsl,imx8mq-usb-phy"; 1260 reg = <0x382f0040 0x40>; 1261 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1262 clock-names = "phy"; 1263 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1264 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1265 assigned-clock-rates = <100000000>; 1266 #phy-cells = <0>; 1267 status = "disabled"; 1268 }; 1269 1270 vpu: video-codec@38300000 { 1271 compatible = "nxp,imx8mq-vpu"; 1272 reg = <0x38300000 0x10000>, 1273 <0x38310000 0x10000>, 1274 <0x38320000 0x10000>; 1275 reg-names = "g1", "g2", "ctrl"; 1276 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1278 interrupt-names = "g1", "g2"; 1279 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1280 <&clk IMX8MQ_CLK_VPU_G2_ROOT>, 1281 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; 1282 clock-names = "g1", "g2", "bus"; 1283 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 1284 <&clk IMX8MQ_CLK_VPU_G2>, 1285 <&clk IMX8MQ_CLK_VPU_BUS>, 1286 <&clk IMX8MQ_VPU_PLL_BYPASS>; 1287 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 1288 <&clk IMX8MQ_VPU_PLL_OUT>, 1289 <&clk IMX8MQ_SYS1_PLL_800M>, 1290 <&clk IMX8MQ_VPU_PLL>; 1291 assigned-clock-rates = <600000000>, <600000000>, 1292 <800000000>, <0>; 1293 power-domains = <&pgc_vpu>; 1294 }; 1295 1296 pcie0: pcie@33800000 { 1297 compatible = "fsl,imx8mq-pcie"; 1298 reg = <0x33800000 0x400000>, 1299 <0x1ff00000 0x80000>; 1300 reg-names = "dbi", "config"; 1301 #address-cells = <3>; 1302 #size-cells = <2>; 1303 device_type = "pci"; 1304 bus-range = <0x00 0xff>; 1305 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1306 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1307 num-lanes = <1>; 1308 num-viewport = <4>; 1309 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1310 interrupt-names = "msi"; 1311 #interrupt-cells = <1>; 1312 interrupt-map-mask = <0 0 0 0x7>; 1313 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1314 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1315 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1316 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1317 fsl,max-link-speed = <2>; 1318 power-domains = <&pgc_pcie>; 1319 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1320 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1321 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1322 reset-names = "pciephy", "apps", "turnoff"; 1323 status = "disabled"; 1324 }; 1325 1326 pcie1: pcie@33c00000 { 1327 compatible = "fsl,imx8mq-pcie"; 1328 reg = <0x33c00000 0x400000>, 1329 <0x27f00000 0x80000>; 1330 reg-names = "dbi", "config"; 1331 #address-cells = <3>; 1332 #size-cells = <2>; 1333 device_type = "pci"; 1334 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ 1335 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1336 num-lanes = <1>; 1337 num-viewport = <4>; 1338 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1339 interrupt-names = "msi"; 1340 #interrupt-cells = <1>; 1341 interrupt-map-mask = <0 0 0 0x7>; 1342 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1343 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1344 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1345 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1346 fsl,max-link-speed = <2>; 1347 power-domains = <&pgc_pcie>; 1348 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1349 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1350 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1351 reset-names = "pciephy", "apps", "turnoff"; 1352 status = "disabled"; 1353 }; 1354 1355 gic: interrupt-controller@38800000 { 1356 compatible = "arm,gic-v3"; 1357 reg = <0x38800000 0x10000>, /* GIC Dist */ 1358 <0x38880000 0xc0000>, /* GICR */ 1359 <0x31000000 0x2000>, /* GICC */ 1360 <0x31010000 0x2000>, /* GICV */ 1361 <0x31020000 0x2000>; /* GICH */ 1362 #interrupt-cells = <3>; 1363 interrupt-controller; 1364 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1365 interrupt-parent = <&gic>; 1366 }; 1367 1368 ddrc: memory-controller@3d400000 { 1369 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1370 reg = <0x3d400000 0x400000>; 1371 clock-names = "core", "pll", "alt", "apb"; 1372 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1373 <&clk IMX8MQ_DRAM_PLL_OUT>, 1374 <&clk IMX8MQ_CLK_DRAM_ALT>, 1375 <&clk IMX8MQ_CLK_DRAM_APB>; 1376 }; 1377 1378 ddr-pmu@3d800000 { 1379 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1380 reg = <0x3d800000 0x400000>; 1381 interrupt-parent = <&gic>; 1382 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1383 }; 1384 }; 1385}; 1386