1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6#include <dt-bindings/bus/ti-sysc.h>
7#include <dt-bindings/clock/omap4.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/omap.h>
11#include <dt-bindings/clock/omap4.h>
12
13/ {
14	compatible = "ti,omap4430", "ti,omap4";
15	interrupt-parent = <&wakeupgen>;
16	#address-cells = <1>;
17	#size-cells = <1>;
18	chosen { };
19
20	aliases {
21		i2c0 = &i2c1;
22		i2c1 = &i2c2;
23		i2c2 = &i2c3;
24		i2c3 = &i2c4;
25		serial0 = &uart1;
26		serial1 = &uart2;
27		serial2 = &uart3;
28		serial3 = &uart4;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu@0 {
36			compatible = "arm,cortex-a9";
37			device_type = "cpu";
38			next-level-cache = <&L2>;
39			reg = <0x0>;
40
41			clocks = <&dpll_mpu_ck>;
42			clock-names = "cpu";
43
44			clock-latency = <300000>; /* From omap-cpufreq driver */
45		};
46		cpu@1 {
47			compatible = "arm,cortex-a9";
48			device_type = "cpu";
49			next-level-cache = <&L2>;
50			reg = <0x1>;
51		};
52	};
53
54	/*
55	 * Note that 4430 needs cross trigger interface (CTI) supported
56	 * before we can configure the interrupts. This means sampling
57	 * events are not supported for pmu. Note that 4460 does not use
58	 * CTI, see also 4460.dtsi.
59	 */
60	pmu {
61		compatible = "arm,cortex-a9-pmu";
62		ti,hwmods = "debugss";
63	};
64
65	gic: interrupt-controller@48241000 {
66		compatible = "arm,cortex-a9-gic";
67		interrupt-controller;
68		#interrupt-cells = <3>;
69		reg = <0x48241000 0x1000>,
70		      <0x48240100 0x0100>;
71		interrupt-parent = <&gic>;
72	};
73
74	L2: l2-cache-controller@48242000 {
75		compatible = "arm,pl310-cache";
76		reg = <0x48242000 0x1000>;
77		cache-unified;
78		cache-level = <2>;
79	};
80
81	local-timer@48240600 {
82		compatible = "arm,cortex-a9-twd-timer";
83		clocks = <&mpu_periphclk>;
84		reg = <0x48240600 0x20>;
85		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
86		interrupt-parent = <&gic>;
87	};
88
89	wakeupgen: interrupt-controller@48281000 {
90		compatible = "ti,omap4-wugen-mpu";
91		interrupt-controller;
92		#interrupt-cells = <3>;
93		reg = <0x48281000 0x1000>;
94		interrupt-parent = <&gic>;
95	};
96
97	/*
98	 * The soc node represents the soc top level view. It is used for IPs
99	 * that are not memory mapped in the MPU view or for the MPU itself.
100	 */
101	soc {
102		compatible = "ti,omap-infra";
103		mpu {
104			compatible = "ti,omap4-mpu";
105			ti,hwmods = "mpu";
106			sram = <&ocmcram>;
107		};
108
109		dsp {
110			compatible = "ti,omap3-c64";
111		};
112
113		iva {
114			compatible = "ti,ivahd";
115			ti,hwmods = "iva";
116		};
117	};
118
119	/*
120	 * XXX: Use a flat representation of the OMAP4 interconnect.
121	 * The real OMAP interconnect network is quite complex.
122	 * Since it will not bring real advantage to represent that in DT for
123	 * the moment, just use a fake OCP bus entry to represent the whole bus
124	 * hierarchy.
125	 */
126	ocp {
127		compatible = "ti,omap4-l3-noc", "simple-bus";
128		#address-cells = <1>;
129		#size-cells = <1>;
130		ranges;
131		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
132		reg = <0x44000000 0x1000>,
133		      <0x44800000 0x2000>,
134		      <0x45000000 0x1000>;
135		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
136			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
137
138		l4_wkup: interconnect@4a300000 {
139		};
140
141		l4_cfg: interconnect@4a000000 {
142		};
143
144		l4_per: interconnect@48000000 {
145		};
146
147		l4_abe: interconnect@40100000 {
148		};
149
150		ocmcram: sram@40304000 {
151			compatible = "mmio-sram";
152			reg = <0x40304000 0xa000>; /* 40k */
153		};
154
155		gpmc: gpmc@50000000 {
156			compatible = "ti,omap4430-gpmc";
157			reg = <0x50000000 0x1000>;
158			#address-cells = <2>;
159			#size-cells = <1>;
160			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
161			dmas = <&sdma 4>;
162			dma-names = "rxtx";
163			gpmc,num-cs = <8>;
164			gpmc,num-waitpins = <4>;
165			ti,hwmods = "gpmc";
166			ti,no-idle-on-init;
167			clocks = <&l3_div_ck>;
168			clock-names = "fck";
169			interrupt-controller;
170			#interrupt-cells = <2>;
171			gpio-controller;
172			#gpio-cells = <2>;
173		};
174
175		target-module@52000000 {
176			compatible = "ti,sysc-omap4", "ti,sysc";
177			ti,hwmods = "iss";
178			reg = <0x52000000 0x4>,
179			      <0x52000010 0x4>;
180			reg-names = "rev", "sysc";
181			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
182			ti,sysc-midle = <SYSC_IDLE_FORCE>,
183					<SYSC_IDLE_NO>,
184					<SYSC_IDLE_SMART>,
185					<SYSC_IDLE_SMART_WKUP>;
186			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
187					<SYSC_IDLE_NO>,
188					<SYSC_IDLE_SMART>,
189					<SYSC_IDLE_SMART_WKUP>;
190			ti,sysc-delay-us = <2>;
191			clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
192			clock-names = "fck";
193			#address-cells = <1>;
194			#size-cells = <1>;
195			ranges = <0 0x52000000 0x1000000>;
196
197			/* No child device binding, driver in staging */
198		};
199
200		target-module@55082000 {
201			compatible = "ti,sysc-omap2", "ti,sysc";
202			reg = <0x55082000 0x4>,
203			      <0x55082010 0x4>,
204			      <0x55082014 0x4>;
205			reg-names = "rev", "sysc", "syss";
206			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
207					<SYSC_IDLE_NO>,
208					<SYSC_IDLE_SMART>;
209			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
210					 SYSC_OMAP2_SOFTRESET |
211					 SYSC_OMAP2_AUTOIDLE)>;
212			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
213			clock-names = "fck";
214			resets = <&prm_core 2>;
215			reset-names = "rstctrl";
216			ranges = <0x0 0x55082000 0x100>;
217			#size-cells = <1>;
218			#address-cells = <1>;
219
220			mmu_ipu: mmu@0 {
221				compatible = "ti,omap4-iommu";
222				reg = <0x0 0x100>;
223				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
224				#iommu-cells = <0>;
225				ti,iommu-bus-err-back;
226			};
227		};
228
229		target-module@4012c000 {
230			compatible = "ti,sysc-omap4", "ti,sysc";
231			reg = <0x4012c000 0x4>,
232			      <0x4012c010 0x4>;
233			reg-names = "rev", "sysc";
234			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
235			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
236					<SYSC_IDLE_NO>,
237					<SYSC_IDLE_SMART>,
238					<SYSC_IDLE_SMART_WKUP>;
239			clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
240			clock-names = "fck";
241			#address-cells = <1>;
242			#size-cells = <1>;
243			ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
244				 <0x4902c000 0x4902c000 0x1000>; /* L3 */
245
246			/* No child device binding or driver in mainline */
247		};
248
249		dmm@4e000000 {
250			compatible = "ti,omap4-dmm";
251			reg = <0x4e000000 0x800>;
252			interrupts = <0 113 0x4>;
253			ti,hwmods = "dmm";
254		};
255
256		emif1: emif@4c000000 {
257			compatible = "ti,emif-4d";
258			reg = <0x4c000000 0x100>;
259			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
260			ti,hwmods = "emif1";
261			ti,no-idle-on-init;
262			phy-type = <1>;
263			hw-caps-read-idle-ctrl;
264			hw-caps-ll-interface;
265			hw-caps-temp-alert;
266		};
267
268		emif2: emif@4d000000 {
269			compatible = "ti,emif-4d";
270			reg = <0x4d000000 0x100>;
271			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
272			ti,hwmods = "emif2";
273			ti,no-idle-on-init;
274			phy-type = <1>;
275			hw-caps-read-idle-ctrl;
276			hw-caps-ll-interface;
277			hw-caps-temp-alert;
278		};
279
280		aes1_target: target-module@4b501000 {
281			compatible = "ti,sysc-omap2", "ti,sysc";
282			reg = <0x4b501080 0x4>,
283			      <0x4b501084 0x4>,
284			      <0x4b501088 0x4>;
285			reg-names = "rev", "sysc", "syss";
286			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
287					 SYSC_OMAP2_AUTOIDLE)>;
288			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
289					<SYSC_IDLE_NO>,
290					<SYSC_IDLE_SMART>,
291					<SYSC_IDLE_SMART_WKUP>;
292			ti,syss-mask = <1>;
293			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
294			clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
295			clock-names = "fck";
296			#address-cells = <1>;
297			#size-cells = <1>;
298			ranges = <0x0 0x4b501000 0x1000>;
299
300			aes1: aes@0 {
301				compatible = "ti,omap4-aes";
302				reg = <0 0xa0>;
303				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
304				dmas = <&sdma 111>, <&sdma 110>;
305				dma-names = "tx", "rx";
306			};
307		};
308
309		aes2_target: target-module@4b701000 {
310			compatible = "ti,sysc-omap2", "ti,sysc";
311			reg = <0x4b701080 0x4>,
312			      <0x4b701084 0x4>,
313			      <0x4b701088 0x4>;
314			reg-names = "rev", "sysc", "syss";
315			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
316					 SYSC_OMAP2_AUTOIDLE)>;
317			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
318					<SYSC_IDLE_NO>,
319					<SYSC_IDLE_SMART>,
320					<SYSC_IDLE_SMART_WKUP>;
321			ti,syss-mask = <1>;
322			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
323			clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
324			clock-names = "fck";
325			#address-cells = <1>;
326			#size-cells = <1>;
327			ranges = <0x0 0x4b701000 0x1000>;
328
329			aes2: aes@0 {
330				compatible = "ti,omap4-aes";
331				reg = <0 0xa0>;
332				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
333				dmas = <&sdma 114>, <&sdma 113>;
334				dma-names = "tx", "rx";
335			};
336		};
337
338		sham_target: target-module@4b100000 {
339			compatible = "ti,sysc-omap3-sham", "ti,sysc";
340			reg = <0x4b100100 0x4>,
341			      <0x4b100110 0x4>,
342			      <0x4b100114 0x4>;
343			reg-names = "rev", "sysc", "syss";
344			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
345					 SYSC_OMAP2_AUTOIDLE)>;
346			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
347					<SYSC_IDLE_NO>,
348					<SYSC_IDLE_SMART>;
349			ti,syss-mask = <1>;
350			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
351			clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
352			clock-names = "fck";
353			#address-cells = <1>;
354			#size-cells = <1>;
355			ranges = <0x0 0x4b100000 0x1000>;
356
357			sham: sham@0 {
358				compatible = "ti,omap4-sham";
359				reg = <0 0x300>;
360				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
361				dmas = <&sdma 119>;
362				dma-names = "rx";
363			};
364		};
365
366		abb_mpu: regulator-abb-mpu {
367			compatible = "ti,abb-v2";
368			regulator-name = "abb_mpu";
369			#address-cells = <0>;
370			#size-cells = <0>;
371			ti,tranxdone-status-mask = <0x80>;
372			clocks = <&sys_clkin_ck>;
373			ti,settling-time = <50>;
374			ti,clock-cycles = <16>;
375
376			status = "disabled";
377		};
378
379		abb_iva: regulator-abb-iva {
380			compatible = "ti,abb-v2";
381			regulator-name = "abb_iva";
382			#address-cells = <0>;
383			#size-cells = <0>;
384			ti,tranxdone-status-mask = <0x80000000>;
385			clocks = <&sys_clkin_ck>;
386			ti,settling-time = <50>;
387			ti,clock-cycles = <16>;
388
389			status = "disabled";
390		};
391
392		target-module@56000000 {
393			compatible = "ti,sysc-omap4", "ti,sysc";
394			reg = <0x5600fe00 0x4>,
395			      <0x5600fe10 0x4>;
396			reg-names = "rev", "sysc";
397			ti,sysc-midle = <SYSC_IDLE_FORCE>,
398					<SYSC_IDLE_NO>,
399					<SYSC_IDLE_SMART>,
400					<SYSC_IDLE_SMART_WKUP>;
401			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
402					<SYSC_IDLE_NO>,
403					<SYSC_IDLE_SMART>,
404					<SYSC_IDLE_SMART_WKUP>;
405			clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
406			clock-names = "fck";
407			#address-cells = <1>;
408			#size-cells = <1>;
409			ranges = <0 0x56000000 0x2000000>;
410
411			/*
412			 * Closed source PowerVR driver, no child device
413			 * binding or driver in mainline
414			 */
415		};
416
417		/*
418		 * DSS is only using l3 mapping without l4 as noted in the TRM
419		 * "10.1.3 DSS Register Manual" for omap4460.
420		 */
421		target-module@58000000 {
422			compatible = "ti,sysc-omap2", "ti,sysc";
423			reg = <0x58000000 4>,
424			      <0x58000014 4>;
425			reg-names = "rev", "syss";
426			ti,syss-mask = <1>;
427			clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
428				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
429				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
430				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
431			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
432			#address-cells = <1>;
433			#size-cells = <1>;
434			ranges = <0 0x58000000 0x1000000>;
435
436			dss: dss@0 {
437				compatible = "ti,omap4-dss";
438				reg = <0 0x80>;
439				status = "disabled";
440				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
441				clock-names = "fck";
442				#address-cells = <1>;
443				#size-cells = <1>;
444				ranges = <0 0 0x1000000>;
445
446				target-module@1000 {
447					compatible = "ti,sysc-omap2", "ti,sysc";
448					reg = <0x1000 0x4>,
449					      <0x1010 0x4>,
450					      <0x1014 0x4>;
451					reg-names = "rev", "sysc", "syss";
452					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
453							<SYSC_IDLE_NO>,
454							<SYSC_IDLE_SMART>;
455					ti,sysc-midle = <SYSC_IDLE_FORCE>,
456							<SYSC_IDLE_NO>,
457							<SYSC_IDLE_SMART>;
458					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
459							 SYSC_OMAP2_ENAWAKEUP |
460							 SYSC_OMAP2_SOFTRESET |
461							 SYSC_OMAP2_AUTOIDLE)>;
462					ti,syss-mask = <1>;
463					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
464						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
465					clock-names = "fck", "sys_clk";
466					#address-cells = <1>;
467					#size-cells = <1>;
468					ranges = <0 0x1000 0x1000>;
469
470					dispc@0 {
471						compatible = "ti,omap4-dispc";
472						reg = <0 0x1000>;
473						interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
474						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
475						clock-names = "fck";
476					};
477				};
478
479				target-module@2000 {
480					compatible = "ti,sysc-omap2", "ti,sysc";
481					reg = <0x2000 0x4>,
482					      <0x2010 0x4>,
483					      <0x2014 0x4>;
484					reg-names = "rev", "sysc", "syss";
485					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
486							<SYSC_IDLE_NO>,
487							<SYSC_IDLE_SMART>;
488					ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
489							 SYSC_OMAP2_AUTOIDLE)>;
490					ti,syss-mask = <1>;
491					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
492						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
493					clock-names = "fck", "sys_clk";
494					#address-cells = <1>;
495					#size-cells = <1>;
496					ranges = <0 0x2000 0x1000>;
497
498					rfbi: encoder@0  {
499						reg = <0 0x1000>;
500						status = "disabled";
501						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
502						clock-names = "fck", "ick";
503					};
504				};
505
506				target-module@3000 {
507					compatible = "ti,sysc-omap2", "ti,sysc";
508					reg = <0x3000 0x4>;
509					reg-names = "rev";
510					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
511					clock-names = "sys_clk";
512					#address-cells = <1>;
513					#size-cells = <1>;
514					ranges = <0 0x3000 0x1000>;
515
516					venc: encoder@0 {
517						compatible = "ti,omap4-venc";
518						reg = <0 0x1000>;
519						status = "disabled";
520						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
521						clock-names = "fck";
522					};
523				};
524
525				target-module@4000 {
526					compatible = "ti,sysc-omap2", "ti,sysc";
527					reg = <0x4000 0x4>,
528					      <0x4010 0x4>,
529					      <0x4014 0x4>;
530					reg-names = "rev", "sysc", "syss";
531					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
532							<SYSC_IDLE_NO>,
533							<SYSC_IDLE_SMART>;
534					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
535							 SYSC_OMAP2_ENAWAKEUP |
536							 SYSC_OMAP2_SOFTRESET |
537							 SYSC_OMAP2_AUTOIDLE)>;
538					ti,syss-mask = <1>;
539					#address-cells = <1>;
540					#size-cells = <1>;
541					ranges = <0 0x4000 0x1000>;
542
543					dsi1: encoder@0 {
544						compatible = "ti,omap4-dsi";
545						reg = <0 0x200>,
546						      <0x200 0x40>,
547						      <0x300 0x20>;
548						reg-names = "proto", "phy", "pll";
549						interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
550						status = "disabled";
551						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
552							 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
553						clock-names = "fck", "sys_clk";
554					};
555				};
556
557				target-module@5000 {
558					compatible = "ti,sysc-omap2", "ti,sysc";
559					reg = <0x5000 0x4>,
560					      <0x5010 0x4>,
561					      <0x5014 0x4>;
562					reg-names = "rev", "sysc", "syss";
563					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
564							<SYSC_IDLE_NO>,
565							<SYSC_IDLE_SMART>;
566					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
567							 SYSC_OMAP2_ENAWAKEUP |
568							 SYSC_OMAP2_SOFTRESET |
569							 SYSC_OMAP2_AUTOIDLE)>;
570					ti,syss-mask = <1>;
571					#address-cells = <1>;
572					#size-cells = <1>;
573					ranges = <0 0x5000 0x1000>;
574
575					dsi2: encoder@0 {
576						compatible = "ti,omap4-dsi";
577						reg = <0 0x200>,
578						      <0x200 0x40>,
579						      <0x300 0x20>;
580						reg-names = "proto", "phy", "pll";
581						interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
582						status = "disabled";
583						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
584						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
585						clock-names = "fck", "sys_clk";
586					};
587				};
588
589				target-module@6000 {
590					compatible = "ti,sysc-omap4", "ti,sysc";
591					reg = <0x6000 0x4>,
592					      <0x6010 0x4>;
593					reg-names = "rev", "sysc";
594					/*
595					 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
596					 * but HDMI audio will fail with them.
597					 */
598					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
599							<SYSC_IDLE_NO>;
600					ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
601					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
602						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
603					clock-names = "fck", "dss_clk";
604					#address-cells = <1>;
605					#size-cells = <1>;
606					ranges = <0 0x6000 0x2000>;
607
608					hdmi: encoder@0 {
609					compatible = "ti,omap4-hdmi";
610						reg = <0 0x200>,
611						      <0x200 0x100>,
612						      <0x300 0x100>,
613						      <0x400 0x1000>;
614						reg-names = "wp", "pll", "phy", "core";
615						interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
616						status = "disabled";
617						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
618						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
619						clock-names = "fck", "sys_clk";
620						dmas = <&sdma 76>;
621						dma-names = "audio_tx";
622					};
623				};
624			};
625		};
626	};
627};
628
629#include "omap4-l4.dtsi"
630#include "omap4-l4-abe.dtsi"
631#include "omap44xx-clocks.dtsi"
632
633&prm {
634	prm_tesla: prm@400 {
635		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
636		reg = <0x400 0x100>;
637		#reset-cells = <1>;
638	};
639
640	prm_core: prm@700 {
641		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
642		reg = <0x700 0x100>;
643		#reset-cells = <1>;
644	};
645
646	prm_ivahd: prm@f00 {
647		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
648		reg = <0xf00 0x100>;
649		#reset-cells = <1>;
650	};
651
652	prm_device: prm@1b00 {
653		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
654		reg = <0x1b00 0x40>;
655		#reset-cells = <1>;
656	};
657};
658