1/*
2 * Device Tree Source for OMAP4460 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#include "omap4.dtsi"
11
12/ {
13	cpus {
14		/* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
15		cpu0: cpu@0 {
16			operating-points = <
17				/* kHz    uV */
18				350000  1025000
19				700000  1200000
20				920000  1313000
21			>;
22			clock-latency = <300000>; /* From legacy driver */
23
24			/* cooling options */
25			#cooling-cells = <2>; /* min followed by max */
26		};
27	};
28
29	pmu {
30		compatible = "arm,cortex-a9-pmu";
31		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
33		ti,hwmods = "debugss";
34	};
35
36	thermal-zones {
37		#include "omap4-cpu-thermal.dtsi"
38	};
39
40	ocp {
41		bandgap: bandgap@4a002260 {
42			reg = <0x4a002260 0x4
43			       0x4a00232C 0x4
44			       0x4a002378 0x18>;
45			compatible = "ti,omap4460-bandgap";
46			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
47			gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
48
49			#thermal-sensor-cells = <0>;
50		};
51
52		abb_mpu: regulator-abb-mpu {
53			status = "okay";
54
55			reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
56			      <0x4A002268 0x4>;
57			reg-names = "base-address", "int-address",
58				    "efuse-address";
59
60			ti,abb_info = <
61			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
62			1025000		0	0	0	0	0
63			1200000		0	0	0	0	0
64			1313000		0	0	0x100000 0x40000 0
65			1375000		1	0	0	0	0
66			1389000		1	0	0	0	0
67			>;
68		};
69
70		abb_iva: regulator-abb-iva {
71			status = "okay";
72
73			reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
74			      <0x4A002268 0x4>;
75			reg-names = "base-address", "int-address",
76				    "efuse-address";
77
78			ti,abb_info = <
79			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
80			950000		0	0	0	0	0
81			1140000		0	0	0	0	0
82			1291000		0	0	0x200000 0	0
83			1375000		1	0	0	0	0
84			1376000		1	0	0	0	0
85			>;
86		};
87	};
88
89};
90
91&cpu_thermal {
92	coefficients = <348 (-9301)>;
93};
94
95/* Only some L4 CFG interconnect ranges are different on 4460 */
96&l4_cfg_segment_300000 {
97	ranges = <0x00000000 0x00300000 0x020000>,	/* ap 67 */
98		 <0x00040000 0x00340000 0x001000>,	/* ap 68 */
99		 <0x00020000 0x00320000 0x004000>,	/* ap 71 */
100		 <0x00024000 0x00324000 0x002000>,	/* ap 72 */
101		 <0x00026000 0x00326000 0x001000>,	/* ap 73 */
102		 <0x00027000 0x00327000 0x001000>,	/* ap 74 */
103		 <0x00028000 0x00328000 0x001000>,	/* ap 75 */
104		 <0x00029000 0x00329000 0x001000>,	/* ap 76 */
105		 <0x00030000 0x00330000 0x010000>,	/* ap 77 */
106		 <0x0002a000 0x0032a000 0x002000>,	/* ap 90 */
107		 <0x0002c000 0x0032c000 0x004000>,	/* ap 91 */
108		 <0x00010000 0x00310000 0x008000>,	/* ap 92 */
109		 <0x00018000 0x00318000 0x004000>,	/* ap 93 */
110		 <0x0001c000 0x0031c000 0x002000>,	/* ap 94 */
111		 <0x0001e000 0x0031e000 0x002000>;	/* ap 95 */
112};
113
114&l4_cfg_target_0 {
115	ranges = <0x00000000 0x00000000 0x00010000>,
116		 <0x00010000 0x00010000 0x00008000>,
117		 <0x00018000 0x00018000 0x00004000>,
118		 <0x0001c000 0x0001c000 0x00002000>,
119		 <0x0001e000 0x0001e000 0x00002000>,
120		 <0x00020000 0x00020000 0x00004000>,
121		 <0x00024000 0x00024000 0x00002000>,
122		 <0x00026000 0x00026000 0x00001000>,
123		 <0x00027000 0x00027000 0x00001000>,
124		 <0x00028000 0x00028000 0x00001000>,
125		 <0x00029000 0x00029000 0x00001000>,
126		 <0x0002a000 0x0002a000 0x00002000>,
127		 <0x0002c000 0x0002c000 0x00004000>,
128		 <0x00030000 0x00030000 0x00010000>;
129};
130
131/include/ "omap446x-clocks.dtsi"
132