1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/rv1108-cru.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	compatible = "rockchip,rv1108";
16
17	interrupt-parent = <&gic>;
18
19	aliases {
20		serial0 = &uart0;
21		serial1 = &uart1;
22		serial2 = &uart2;
23		spi0	= &sfc;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu0: cpu@f00 {
31			device_type = "cpu";
32			compatible = "arm,cortex-a7";
33			reg = <0xf00>;
34		};
35	};
36
37	arm-pmu {
38		compatible = "arm,cortex-a7-pmu";
39		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
40	};
41
42	timer {
43		compatible = "arm,armv7-timer";
44		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
45			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
46		clock-frequency = <24000000>;
47	};
48
49	xin24m: oscillator {
50		compatible = "fixed-clock";
51		clock-frequency = <24000000>;
52		clock-output-names = "xin24m";
53		#clock-cells = <0>;
54	};
55
56	amba {
57		compatible = "simple-bus";
58		#address-cells = <1>;
59		#size-cells = <1>;
60		ranges;
61
62		pdma: pdma@102a0000 {
63			compatible = "arm,pl330", "arm,primecell";
64			reg = <0x102a0000 0x4000>;
65			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
66			#dma-cells = <1>;
67			arm,pl330-broken-no-flushp;
68			clocks = <&cru ACLK_DMAC>;
69			clock-names = "apb_pclk";
70		};
71	};
72
73	bus_intmem@10080000 {
74		compatible = "mmio-sram";
75		reg = <0x10080000 0x2000>;
76		#address-cells = <1>;
77		#size-cells = <1>;
78		ranges = <0 0x10080000 0x2000>;
79	};
80
81	uart2: serial@10210000 {
82		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
83		reg = <0x10210000 0x100>;
84		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
85		reg-shift = <2>;
86		reg-io-width = <4>;
87		clock-frequency = <24000000>;
88		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
89		clock-names = "baudclk", "apb_pclk";
90		pinctrl-names = "default";
91		pinctrl-0 = <&uart2m0_xfer>;
92		status = "disabled";
93	};
94
95	uart1: serial@10220000 {
96		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
97		reg = <0x10220000 0x100>;
98		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
99		reg-shift = <2>;
100		reg-io-width = <4>;
101		clock-frequency = <24000000>;
102		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
103		clock-names = "baudclk", "apb_pclk";
104		pinctrl-names = "default";
105		pinctrl-0 = <&uart1_xfer>;
106		status = "disabled";
107	};
108
109	uart0: serial@10230000 {
110		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
111		reg = <0x10230000 0x100>;
112		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
113		reg-shift = <2>;
114		reg-io-width = <4>;
115		clock-frequency = <24000000>;
116		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
117		clock-names = "baudclk", "apb_pclk";
118		pinctrl-names = "default";
119		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
120		status = "disabled";
121	};
122
123	grf: syscon@10300000 {
124		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
125		reg = <0x10300000 0x1000>;
126		#address-cells = <1>;
127		#size-cells = <1>;
128
129		u2phy: usb2-phy@100 {
130			compatible = "rockchip,rv1108-usb2phy";
131			reg = <0x100 0x0c>;
132			clocks = <&cru SCLK_USBPHY>;
133			clock-names = "phyclk";
134			#clock-cells = <0>;
135			clock-output-names = "usbphy";
136			rockchip,usbgrf = <&usbgrf>;
137			status = "disabled";
138
139			u2phy_otg: otg-port {
140				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
141				interrupt-names = "otg-mux";
142				#phy-cells = <0>;
143				status = "disabled";
144			};
145
146			u2phy_host: host-port {
147				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
148				interrupt-names = "linestate";
149				#phy-cells = <0>;
150				status = "disabled";
151			};
152		};
153	};
154
155	saradc: saradc@1038c000 {
156		compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
157		reg = <0x1038c000 0x100>;
158		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
159		#io-channel-cells = <1>;
160		clock-frequency = <1000000>;
161		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
162		clock-names = "saradc", "apb_pclk";
163		status = "disabled";
164	};
165
166	pmugrf: syscon@20060000 {
167		compatible = "rockchip,rv1108-pmugrf", "syscon";
168		reg = <0x20060000 0x1000>;
169	};
170
171	usbgrf: syscon@202a0000 {
172		compatible = "rockchip,rv1108-usbgrf", "syscon";
173		reg = <0x202a0000 0x1000>;
174	};
175
176	cru: clock-controller@20200000 {
177		compatible = "rockchip,rv1108-cru";
178		reg = <0x20200000 0x1000>;
179		rockchip,grf = <&grf>;
180		#clock-cells = <1>;
181		#reset-cells = <1>;
182	};
183
184	emmc: dwmmc@30110000 {
185		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
186		clock-freq-min-max = <400000 150000000>;
187		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
188			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
189		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
190		fifo-depth = <0x100>;
191		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
192		reg = <0x30110000 0x4000>;
193		status = "disabled";
194	};
195
196	sdio: dwmmc@30120000 {
197		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
198		clock-freq-min-max = <400000 150000000>;
199		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
200			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
201		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
202		fifo-depth = <0x100>;
203		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
204		reg = <0x30120000 0x4000>;
205		status = "disabled";
206	};
207
208	sdmmc: dwmmc@30130000 {
209		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
210		clock-freq-min-max = <400000 100000000>;
211		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214		fifo-depth = <0x100>;
215		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
216		reg = <0x30130000 0x4000>;
217		status = "disabled";
218	};
219
220	usb_host_ehci: usb@30140000 {
221		compatible = "generic-ehci";
222		reg = <0x30140000 0x20000>;
223		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
224		status = "disabled";
225	};
226
227	usb_host_ohci: usb@30160000 {
228		compatible = "generic-ohci";
229		reg = <0x30160000 0x20000>;
230		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
231		status = "disabled";
232	};
233
234	usb20_otg: usb@30180000 {
235		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
236			     "snps,dwc2";
237		reg = <0x30180000 0x40000>;
238		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
239		clocks = <&cru HCLK_OTG>;
240		clock-names = "otg";
241		dr_mode = "otg";
242		g-np-tx-fifo-size = <16>;
243		g-rx-fifo-size = <280>;
244		g-tx-fifo-size = <256 128 128 64 32 16>;
245		g-use-dma;
246		phys = <&u2phy_otg>;
247		phy-names = "usb2-phy";
248		status = "disabled";
249	};
250
251	sfc: sfc@301c0000 {
252		compatible = "rockchip,sfc";
253		reg = <0x301c0000 0x200>;
254		#address-cells = <1>;
255		#size-cells = <0>;
256		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
257		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
258		clock-names = "clk_sfc", "hclk_sfc";
259		pinctrl-0 = <&sfc_pins>;
260		pinctrl-names = "default";
261		status = "disabled";
262        };
263
264	gmac: ethernet@30200000 {
265		compatible = "rockchip,rv1108-gmac";
266		reg = <0x30200000 0x10000>;
267		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
268		interrupt-names = "macirq";
269		rockchip,grf = <&grf>;
270		clocks = <&cru SCLK_MAC>,
271			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
272			<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
273			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
274                clock-names = "stmmaceth",
275                        "mac_clk_rx", "mac_clk_tx",
276                        "clk_mac_ref", "clk_mac_refout",
277                        "aclk_mac", "pclk_mac";
278		pinctrl-names = "default";
279		pinctrl-0 = <&rmii_pins>;
280		phy-mode = "rmii";
281		max-speed = <100>;
282		status = "disabled";
283	};
284
285	gic: interrupt-controller@32010000 {
286		compatible = "arm,gic-400";
287		interrupt-controller;
288		#interrupt-cells = <3>;
289		#address-cells = <0>;
290
291		reg = <0x32011000 0x1000>,
292		      <0x32012000 0x1000>,
293		      <0x32014000 0x2000>,
294		      <0x32016000 0x2000>;
295		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
296	};
297
298	pinctrl: pinctrl {
299		compatible = "rockchip,rv1108-pinctrl";
300		rockchip,grf = <&grf>;
301		rockchip,pmu = <&pmugrf>;
302		#address-cells = <1>;
303		#size-cells = <1>;
304		ranges;
305
306		gpio0: gpio0@20030000 {
307			compatible = "rockchip,gpio-bank";
308			reg = <0x20030000 0x100>;
309			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
310			clocks = <&xin24m>;
311
312			gpio-controller;
313			#gpio-cells = <2>;
314
315			interrupt-controller;
316			#interrupt-cells = <2>;
317		};
318
319		gpio1: gpio1@10310000 {
320			compatible = "rockchip,gpio-bank";
321			reg = <0x10310000 0x100>;
322			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
323			clocks = <&xin24m>;
324
325			gpio-controller;
326			#gpio-cells = <2>;
327
328			interrupt-controller;
329			#interrupt-cells = <2>;
330		};
331
332		gpio2: gpio2@10320000 {
333			compatible = "rockchip,gpio-bank";
334			reg = <0x10320000 0x100>;
335			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
336			clocks = <&xin24m>;
337
338			gpio-controller;
339			#gpio-cells = <2>;
340
341			interrupt-controller;
342			#interrupt-cells = <2>;
343		};
344
345		gpio3: gpio3@10330000 {
346			compatible = "rockchip,gpio-bank";
347			reg = <0x10330000 0x100>;
348			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
349			clocks = <&xin24m>;
350
351			gpio-controller;
352			#gpio-cells = <2>;
353
354			interrupt-controller;
355			#interrupt-cells = <2>;
356		};
357
358		pcfg_pull_up: pcfg-pull-up {
359			bias-pull-up;
360		};
361
362		pcfg_pull_down: pcfg-pull-down {
363			bias-pull-down;
364		};
365
366		pcfg_pull_none: pcfg-pull-none {
367			bias-disable;
368		};
369
370		pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
371			drive-strength = <8>;
372		};
373
374		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
375			drive-strength = <12>;
376		};
377
378		pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
379			bias-pull-up;
380			drive-strength = <8>;
381		};
382
383		pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
384			drive-strength = <4>;
385		};
386
387		pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
388			bias-pull-up;
389			drive-strength = <4>;
390		};
391
392		pcfg_output_high: pcfg-output-high {
393			output-high;
394		};
395
396		pcfg_output_low: pcfg-output-low {
397			output-low;
398		};
399
400		pcfg_input_high: pcfg-input-high {
401			bias-pull-up;
402			input-enable;
403		};
404
405		gmac {
406			rmii_pins: rmii-pins {
407				rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
408						<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
409						<1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
410						<1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
411						<1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
412						<1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
413						<1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
414						<1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
415						<1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
416						<1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
417			};
418		};
419
420		i2c1 {
421			i2c1_xfer: i2c1-xfer {
422				rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
423						<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
424			};
425		};
426
427		i2c2m1 {
428			i2c2m1_xfer: i2c2m1-xfer {
429				rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
430						<0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
431			};
432
433			i2c2m1_gpio: i2c2m1-gpio {
434				rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
435						<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
436			};
437		};
438
439		i2c2m05v {
440			i2c2m05v_xfer: i2c2m05v-xfer {
441				rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
442						<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
443			};
444
445			i2c2m05v_gpio: i2c2m05v-gpio {
446				rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
447						<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
448			};
449		};
450
451		i2c3 {
452			i2c3_xfer: i2c3-xfer {
453				rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
454						<0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
455			};
456		};
457
458		sfc {
459			sfc_pins: sfc-pins {
460				rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
461						<2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
462						<2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
463						<2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
464						<2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
465						<2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
466			};
467		};
468
469		emmc {
470			emmc_clk: emmc-clk {
471				rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
472			};
473
474			emmc_cmd: emmc-cmd {
475				rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
476			};
477
478			emmc_pwren: emmc-pwren {
479				rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
480			};
481
482			emmc_bus1: emmc-bus1 {
483				rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
484			};
485
486			emmc_bus8: emmc-bus8 {
487				rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
488						<2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
489						<2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
490						<2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
491						<2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
492						<2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
493						<2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
494						<2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
495			};
496		};
497
498		sdmmc {
499			sdmmc_clk: sdmmc-clk {
500				rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
501			};
502
503			sdmmc_cmd: sdmmc-cmd {
504				rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
505			};
506
507			sdmmc_cd: sdmmc-cd {
508				rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
509			};
510
511			sdmmc_bus1: sdmmc-bus1 {
512				rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
513			};
514
515			sdmmc_bus4: sdmmc-bus4 {
516				rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
517						<3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
518						<3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
519						<3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
520			};
521		};
522
523		uart0 {
524			uart0_xfer: uart0-xfer {
525				rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
526						<3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
527			};
528
529			uart0_cts: uart0-cts {
530				rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
531			};
532
533			uart0_rts: uart0-rts {
534				rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
535			};
536
537			uart0_rts_gpio: uart0-rts-gpio {
538				rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
539			};
540		};
541
542		uart1 {
543			uart1_xfer: uart1-xfer {
544				rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
545						<1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
546			};
547
548			uart1_cts: uart1-cts {
549				rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
550			};
551
552			uart01rts: uart1-rts {
553				rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
554			};
555		};
556
557		uart2m0 {
558			uart2m0_xfer: uart2m0-xfer {
559				rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
560						<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
561			};
562		};
563
564		uart2m1 {
565			uart2m1_xfer: uart2m1-xfer {
566				rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
567						<3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
568			};
569		};
570
571		uart2_5v {
572			uart2_5v_cts: uart2_5v-cts {
573				rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
574			};
575
576			uart2_5v_rts: uart2_5v-rts {
577				rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
578			};
579		};
580	};
581};
582