1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Andreas Färber
4 */
5
6#include <dt-bindings/clock/actions,s700-cmu.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/actions,s700-reset.h>
9
10/ {
11	compatible = "actions,s700";
12	interrupt-parent = <&gic>;
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <2>;
18		#size-cells = <0>;
19
20		cpu0: cpu@0 {
21			device_type = "cpu";
22			compatible = "arm,cortex-a53";
23			reg = <0x0 0x0>;
24			enable-method = "psci";
25		};
26
27		cpu1: cpu@1 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			reg = <0x0 0x1>;
31			enable-method = "psci";
32		};
33
34		cpu2: cpu@2 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a53";
37			reg = <0x0 0x2>;
38			enable-method = "psci";
39		};
40
41		cpu3: cpu@3 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			reg = <0x0 0x3>;
45			enable-method = "psci";
46		};
47	};
48
49	reserved-memory {
50		#address-cells = <2>;
51		#size-cells = <2>;
52		ranges;
53
54		secmon@1f000000 {
55			reg = <0x0 0x1f000000 0x0 0x1000000>;
56			no-map;
57		};
58	};
59
60	psci {
61		compatible = "arm,psci-0.2";
62		method = "smc";
63	};
64
65	arm-pmu {
66		compatible = "arm,cortex-a53-pmu";
67		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
68		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
69		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
70		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
71		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
72	};
73
74	timer {
75		compatible = "arm,armv8-timer";
76		interrupts = <GIC_PPI 13
77			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
78			     <GIC_PPI 14
79			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
80			     <GIC_PPI 11
81			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82			     <GIC_PPI 10
83			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
84	};
85
86	hosc: hosc {
87		compatible = "fixed-clock";
88		clock-frequency = <24000000>;
89		#clock-cells = <0>;
90	};
91
92	losc: losc {
93		compatible = "fixed-clock";
94		clock-frequency = <32768>;
95		#clock-cells = <0>;
96	};
97
98	soc {
99		compatible = "simple-bus";
100		#address-cells = <2>;
101		#size-cells = <2>;
102		ranges;
103
104		gic: interrupt-controller@e00f1000 {
105			compatible = "arm,gic-400";
106			reg = <0x0 0xe00f1000 0x0 0x1000>,
107			      <0x0 0xe00f2000 0x0 0x2000>,
108			      <0x0 0xe00f4000 0x0 0x2000>,
109			      <0x0 0xe00f6000 0x0 0x2000>;
110			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
111			interrupt-controller;
112			#interrupt-cells = <3>;
113		};
114
115		uart0: serial@e0120000 {
116			compatible = "actions,s900-uart", "actions,owl-uart";
117			reg = <0x0 0xe0120000 0x0 0x2000>;
118			clocks = <&cmu CLK_UART0>;
119			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
120			status = "disabled";
121		};
122
123		uart1: serial@e0122000 {
124			compatible = "actions,s900-uart", "actions,owl-uart";
125			reg = <0x0 0xe0122000 0x0 0x2000>;
126			clocks = <&cmu CLK_UART1>;
127			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
128			status = "disabled";
129		};
130
131		uart2: serial@e0124000 {
132			compatible = "actions,s900-uart", "actions,owl-uart";
133			reg = <0x0 0xe0124000 0x0 0x2000>;
134			clocks = <&cmu CLK_UART2>;
135			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
136			status = "disabled";
137		};
138
139		uart3: serial@e0126000 {
140			compatible = "actions,s900-uart", "actions,owl-uart";
141			reg = <0x0 0xe0126000 0x0 0x2000>;
142			clocks = <&cmu CLK_UART3>;
143			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
144			status = "disabled";
145		};
146
147		uart4: serial@e0128000 {
148			compatible = "actions,s900-uart", "actions,owl-uart";
149			reg = <0x0 0xe0128000 0x0 0x2000>;
150			clocks = <&cmu CLK_UART4>;
151			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
152			status = "disabled";
153		};
154
155		uart5: serial@e012a000 {
156			compatible = "actions,s900-uart", "actions,owl-uart";
157			reg = <0x0 0xe012a000 0x0 0x2000>;
158			clocks = <&cmu CLK_UART5>;
159			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
160			status = "disabled";
161		};
162
163		uart6: serial@e012c000 {
164			compatible = "actions,s900-uart", "actions,owl-uart";
165			reg = <0x0 0xe012c000 0x0 0x2000>;
166			clocks = <&cmu CLK_UART6>;
167			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
168			status = "disabled";
169		};
170
171		cmu: clock-controller@e0168000 {
172			compatible = "actions,s700-cmu";
173			reg = <0x0 0xe0168000 0x0 0x1000>;
174			clocks = <&hosc>, <&losc>;
175			#clock-cells = <1>;
176			#reset-cells = <1>;
177		};
178
179		i2c0: i2c@e0170000 {
180			compatible = "actions,s700-i2c";
181			reg = <0 0xe0170000 0 0x1000>;
182			clocks = <&cmu CLK_I2C0>;
183			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
184			#address-cells = <1>;
185			#size-cells = <0>;
186			status = "disabled";
187		};
188
189		i2c1: i2c@e0174000 {
190			compatible = "actions,s700-i2c";
191			reg = <0 0xe0174000 0 0x1000>;
192			clocks = <&cmu CLK_I2C1>;
193			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
194			#address-cells = <1>;
195			#size-cells = <0>;
196			status = "disabled";
197		};
198
199		i2c2: i2c@e0178000 {
200			compatible = "actions,s700-i2c";
201			reg = <0 0xe0178000 0 0x1000>;
202			clocks = <&cmu CLK_I2C2>;
203			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
204			#address-cells = <1>;
205			#size-cells = <0>;
206			status = "disabled";
207		};
208
209		i2c3: i2c@e017c000 {
210			compatible = "actions,s700-i2c";
211			reg = <0 0xe017c000 0 0x1000>;
212			clocks = <&cmu CLK_I2C3>;
213			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
214			#address-cells = <1>;
215			#size-cells = <0>;
216			status = "disabled";
217		};
218
219		sps: power-controller@e01b0100 {
220			compatible = "actions,s700-sps";
221			reg = <0x0 0xe01b0100 0x0 0x100>;
222			#power-domain-cells = <1>;
223		};
224
225		timer: timer@e024c000 {
226			compatible = "actions,s700-timer";
227			reg = <0x0 0xe024c000 0x0 0x4000>;
228			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
229			interrupt-names = "timer1";
230		};
231
232		pinctrl: pinctrl@e01b0000 {
233			compatible = "actions,s700-pinctrl";
234			reg = <0x0 0xe01b0000 0x0 0x1000>;
235			clocks = <&cmu CLK_GPIO>;
236			gpio-controller;
237			gpio-ranges = <&pinctrl 0 0 136>;
238			#gpio-cells = <2>;
239			interrupt-controller;
240			#interrupt-cells = <2>;
241			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
242				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
243				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
244				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
245				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
246		};
247	};
248};
249