1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Intel Arria 10 SoCFPGA configuration 4 */ 5 6 #ifndef __SOCFPGA_ARRIA10_CONFIG_H__ 7 #define __SOCFPGA_ARRIA10_CONFIG_H__ 8 9 /* Clocks */ 10 #define CB_INTOSC_LS_CLK_HZ 60000000 11 #define EMAC0_CLK_HZ 250000000 12 #define EMAC1_CLK_HZ 250000000 13 #define EMAC2_CLK_HZ 250000000 14 #define EOSC1_CLK_HZ 25000000 15 #define F2H_FREE_CLK_HZ 200000000 16 #define H2F_USER0_CLK_HZ 400000000 17 #define H2F_USER1_CLK_HZ 400000000 18 #define L3_MAIN_FREE_CLK_HZ 200000000 19 #define SDMMC_CLK_HZ 200000000 20 #define TPIU_CLK_HZ 100000000 21 #define MAINPLLGRP_CNTR15CLK_CNT 900 22 #define MAINPLLGRP_CNTR2CLK_CNT 900 23 #define MAINPLLGRP_CNTR3CLK_CNT 900 24 #define MAINPLLGRP_CNTR4CLK_CNT 900 25 #define MAINPLLGRP_CNTR5CLK_CNT 900 26 #define MAINPLLGRP_CNTR6CLK_CNT 900 27 #define MAINPLLGRP_CNTR7CLK_CNT 900 28 #define MAINPLLGRP_CNTR7CLK_SRC 0 29 #define MAINPLLGRP_CNTR8CLK_CNT 900 30 #define MAINPLLGRP_CNTR9CLK_CNT 900 31 #define MAINPLLGRP_CNTR9CLK_SRC 0 32 #define MAINPLLGRP_MPUCLK_CNT 0 33 #define MAINPLLGRP_MPUCLK_SRC 0 34 #define MAINPLLGRP_NOCCLK_CNT 0 35 #define MAINPLLGRP_NOCCLK_SRC 0 36 #define MAINPLLGRP_NOCDIV_CSATCLK 0 37 #define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 38 #define MAINPLLGRP_NOCDIV_CSTRACECLK 1 39 #define MAINPLLGRP_NOCDIV_L4MAINCLK 0 40 #define MAINPLLGRP_NOCDIV_L4MPCLK 0 41 #define MAINPLLGRP_NOCDIV_L4SPCLK 2 42 #define MAINPLLGRP_VCO0_PSRC 0 43 #define MAINPLLGRP_VCO1_DENOM 1 44 #define MAINPLLGRP_VCO1_NUMER 191 45 #define PERPLLGRP_CNTR2CLK_CNT 7 46 #define PERPLLGRP_CNTR2CLK_SRC 1 47 #define PERPLLGRP_CNTR3CLK_CNT 900 48 #define PERPLLGRP_CNTR3CLK_SRC 1 49 #define PERPLLGRP_CNTR4CLK_CNT 19 50 #define PERPLLGRP_CNTR4CLK_SRC 1 51 #define PERPLLGRP_CNTR5CLK_CNT 499 52 #define PERPLLGRP_CNTR5CLK_SRC 1 53 #define PERPLLGRP_CNTR6CLK_CNT 9 54 #define PERPLLGRP_CNTR6CLK_SRC 1 55 #define PERPLLGRP_CNTR7CLK_CNT 900 56 #define PERPLLGRP_CNTR8CLK_CNT 900 57 #define PERPLLGRP_CNTR8CLK_SRC 0 58 #define PERPLLGRP_CNTR9CLK_CNT 900 59 #define PERPLLGRP_EMACCTL_EMAC0SEL 0 60 #define PERPLLGRP_EMACCTL_EMAC1SEL 0 61 #define PERPLLGRP_EMACCTL_EMAC2SEL 0 62 #define PERPLLGRP_GPIODIV_GPIODBCLK 32000 63 #define PERPLLGRP_VCO0_PSRC 0 64 #define PERPLLGRP_VCO1_DENOM 1 65 #define PERPLLGRP_VCO1_NUMER 159 66 #define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 67 #define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 68 #define CLKMGR_TESTIOCTRL_PERICLKSEL 8 69 #define ALTERAGRP_MPUCLK_MAINCNT 1 70 #define ALTERAGRP_MPUCLK_PERICNT 900 71 #define ALTERAGRP_NOCCLK_MAINCNT 11 72 #define ALTERAGRP_NOCCLK_PERICNT 900 73 #define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ 74 (ALTERAGRP_MPUCLK_MAINCNT)) 75 #define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ 76 (ALTERAGRP_NOCCLK_MAINCNT)) 77 78 /* Pin Mux Configuration */ 79 #define CONFIG_IO_10_INPUT_BUF_EN 0 80 #define CONFIG_IO_10_PD_DRV_STRG 0 81 #define CONFIG_IO_10_PD_SLW_RT 0 82 #define CONFIG_IO_10_PU_DRV_STRG 0 83 #define CONFIG_IO_10_PU_SLW_RT 0 84 #define CONFIG_IO_10_RTRIM 1 85 #define CONFIG_IO_10_WK_PU_EN 1 86 #define CONFIG_IO_11_INPUT_BUF_EN 0 87 #define CONFIG_IO_11_PD_DRV_STRG 0 88 #define CONFIG_IO_11_PD_SLW_RT 0 89 #define CONFIG_IO_11_PU_DRV_STRG 0 90 #define CONFIG_IO_11_PU_SLW_RT 0 91 #define CONFIG_IO_11_RTRIM 1 92 #define CONFIG_IO_11_WK_PU_EN 1 93 #define CONFIG_IO_12_INPUT_BUF_EN 1 94 #define CONFIG_IO_12_PD_DRV_STRG 10 95 #define CONFIG_IO_12_PD_SLW_RT 1 96 #define CONFIG_IO_12_PU_DRV_STRG 8 97 #define CONFIG_IO_12_PU_SLW_RT 1 98 #define CONFIG_IO_12_RTRIM 1 99 #define CONFIG_IO_12_WK_PU_EN 1 100 #define CONFIG_IO_13_INPUT_BUF_EN 1 101 #define CONFIG_IO_13_PD_DRV_STRG 10 102 #define CONFIG_IO_13_PD_SLW_RT 1 103 #define CONFIG_IO_13_PU_DRV_STRG 8 104 #define CONFIG_IO_13_PU_SLW_RT 1 105 #define CONFIG_IO_13_RTRIM 1 106 #define CONFIG_IO_13_WK_PU_EN 1 107 #define CONFIG_IO_14_INPUT_BUF_EN 1 108 #define CONFIG_IO_14_PD_DRV_STRG 10 109 #define CONFIG_IO_14_PD_SLW_RT 1 110 #define CONFIG_IO_14_PU_DRV_STRG 8 111 #define CONFIG_IO_14_PU_SLW_RT 1 112 #define CONFIG_IO_14_RTRIM 1 113 #define CONFIG_IO_14_WK_PU_EN 1 114 #define CONFIG_IO_15_INPUT_BUF_EN 1 115 #define CONFIG_IO_15_PD_DRV_STRG 10 116 #define CONFIG_IO_15_PD_SLW_RT 1 117 #define CONFIG_IO_15_PU_DRV_STRG 8 118 #define CONFIG_IO_15_PU_SLW_RT 1 119 #define CONFIG_IO_15_RTRIM 1 120 #define CONFIG_IO_15_WK_PU_EN 1 121 #define CONFIG_IO_16_INPUT_BUF_EN 0 122 #define CONFIG_IO_16_PD_DRV_STRG 10 123 #define CONFIG_IO_16_PD_SLW_RT 1 124 #define CONFIG_IO_16_PU_DRV_STRG 8 125 #define CONFIG_IO_16_PU_SLW_RT 1 126 #define CONFIG_IO_16_RTRIM 1 127 #define CONFIG_IO_16_WK_PU_EN 0 128 #define CONFIG_IO_17_INPUT_BUF_EN 1 129 #define CONFIG_IO_17_PD_DRV_STRG 10 130 #define CONFIG_IO_17_PD_SLW_RT 1 131 #define CONFIG_IO_17_PU_DRV_STRG 8 132 #define CONFIG_IO_17_PU_SLW_RT 1 133 #define CONFIG_IO_17_RTRIM 1 134 #define CONFIG_IO_17_WK_PU_EN 0 135 #define CONFIG_IO_1_INPUT_BUF_EN 1 136 #define CONFIG_IO_1_PD_DRV_STRG 10 137 #define CONFIG_IO_1_PD_SLW_RT 0 138 #define CONFIG_IO_1_PU_DRV_STRG 8 139 #define CONFIG_IO_1_PU_SLW_RT 0 140 #define CONFIG_IO_1_RTRIM 1 141 #define CONFIG_IO_1_WK_PU_EN 1 142 #define CONFIG_IO_2_INPUT_BUF_EN 1 143 #define CONFIG_IO_2_PD_DRV_STRG 10 144 #define CONFIG_IO_2_PD_SLW_RT 0 145 #define CONFIG_IO_2_PU_DRV_STRG 8 146 #define CONFIG_IO_2_PU_SLW_RT 0 147 #define CONFIG_IO_2_RTRIM 1 148 #define CONFIG_IO_2_WK_PU_EN 1 149 #define CONFIG_IO_3_INPUT_BUF_EN 1 150 #define CONFIG_IO_3_PD_DRV_STRG 10 151 #define CONFIG_IO_3_PD_SLW_RT 0 152 #define CONFIG_IO_3_PU_DRV_STRG 8 153 #define CONFIG_IO_3_PU_SLW_RT 0 154 #define CONFIG_IO_3_RTRIM 1 155 #define CONFIG_IO_3_WK_PU_EN 1 156 #define CONFIG_IO_4_INPUT_BUF_EN 1 157 #define CONFIG_IO_4_PD_DRV_STRG 10 158 #define CONFIG_IO_4_PD_SLW_RT 1 159 #define CONFIG_IO_4_PU_DRV_STRG 8 160 #define CONFIG_IO_4_PU_SLW_RT 1 161 #define CONFIG_IO_4_RTRIM 1 162 #define CONFIG_IO_4_WK_PU_EN 0 163 #define CONFIG_IO_5_INPUT_BUF_EN 1 164 #define CONFIG_IO_5_PD_DRV_STRG 10 165 #define CONFIG_IO_5_PD_SLW_RT 1 166 #define CONFIG_IO_5_PU_DRV_STRG 8 167 #define CONFIG_IO_5_PU_SLW_RT 1 168 #define CONFIG_IO_5_RTRIM 1 169 #define CONFIG_IO_5_WK_PU_EN 0 170 #define CONFIG_IO_6_INPUT_BUF_EN 0 171 #define CONFIG_IO_6_PD_DRV_STRG 10 172 #define CONFIG_IO_6_PD_SLW_RT 1 173 #define CONFIG_IO_6_PU_DRV_STRG 8 174 #define CONFIG_IO_6_PU_SLW_RT 1 175 #define CONFIG_IO_6_RTRIM 1 176 #define CONFIG_IO_6_WK_PU_EN 0 177 #define CONFIG_IO_7_INPUT_BUF_EN 1 178 #define CONFIG_IO_7_PD_DRV_STRG 10 179 #define CONFIG_IO_7_PD_SLW_RT 1 180 #define CONFIG_IO_7_PU_DRV_STRG 8 181 #define CONFIG_IO_7_PU_SLW_RT 1 182 #define CONFIG_IO_7_RTRIM 1 183 #define CONFIG_IO_7_WK_PU_EN 0 184 #define CONFIG_IO_8_INPUT_BUF_EN 1 185 #define CONFIG_IO_8_PD_DRV_STRG 10 186 #define CONFIG_IO_8_PD_SLW_RT 1 187 #define CONFIG_IO_8_PU_DRV_STRG 8 188 #define CONFIG_IO_8_PU_SLW_RT 1 189 #define CONFIG_IO_8_RTRIM 1 190 #define CONFIG_IO_8_WK_PU_EN 0 191 #define CONFIG_IO_9_INPUT_BUF_EN 1 192 #define CONFIG_IO_9_PD_DRV_STRG 10 193 #define CONFIG_IO_9_PD_SLW_RT 1 194 #define CONFIG_IO_9_PU_DRV_STRG 8 195 #define CONFIG_IO_9_PU_SLW_RT 1 196 #define CONFIG_IO_9_RTRIM 1 197 #define CONFIG_IO_9_WK_PU_EN 0 198 #define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1 199 #define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1 200 #define PINMUX_DEDICATED_IO_10_SEL 10 201 #define PINMUX_DEDICATED_IO_11_SEL 10 202 #define PINMUX_DEDICATED_IO_12_SEL 8 203 #define PINMUX_DEDICATED_IO_13_SEL 8 204 #define PINMUX_DEDICATED_IO_14_SEL 8 205 #define PINMUX_DEDICATED_IO_15_SEL 8 206 #define PINMUX_DEDICATED_IO_16_SEL 13 207 #define PINMUX_DEDICATED_IO_17_SEL 13 208 #define PINMUX_DEDICATED_IO_4_SEL 8 209 #define PINMUX_DEDICATED_IO_5_SEL 8 210 #define PINMUX_DEDICATED_IO_6_SEL 8 211 #define PINMUX_DEDICATED_IO_7_SEL 8 212 #define PINMUX_DEDICATED_IO_8_SEL 8 213 #define PINMUX_DEDICATED_IO_9_SEL 8 214 #define PINMUX_I2C0_USEFPGA_SEL 0 215 #define PINMUX_I2C1_USEFPGA_SEL 0 216 #define PINMUX_I2CEMAC0_USEFPGA_SEL 0 217 #define PINMUX_I2CEMAC1_USEFPGA_SEL 0 218 #define PINMUX_I2CEMAC2_USEFPGA_SEL 0 219 #define PINMUX_NAND_USEFPGA_SEL 0 220 #define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0 221 #define PINMUX_QSPI_USEFPGA_SEL 0 222 #define PINMUX_RGMII0_USEFPGA_SEL 0 223 #define PINMUX_RGMII1_USEFPGA_SEL 0 224 #define PINMUX_RGMII2_USEFPGA_SEL 0 225 #define PINMUX_SDMMC_USEFPGA_SEL 0 226 #define PINMUX_SHARED_IO_Q1_10_SEL 8 227 #define PINMUX_SHARED_IO_Q1_11_SEL 8 228 #define PINMUX_SHARED_IO_Q1_12_SEL 8 229 #define PINMUX_SHARED_IO_Q1_1_SEL 8 230 #define PINMUX_SHARED_IO_Q1_2_SEL 8 231 #define PINMUX_SHARED_IO_Q1_3_SEL 8 232 #define PINMUX_SHARED_IO_Q1_4_SEL 8 233 #define PINMUX_SHARED_IO_Q1_5_SEL 8 234 #define PINMUX_SHARED_IO_Q1_6_SEL 8 235 #define PINMUX_SHARED_IO_Q1_7_SEL 8 236 #define PINMUX_SHARED_IO_Q1_8_SEL 8 237 #define PINMUX_SHARED_IO_Q1_9_SEL 8 238 #define PINMUX_SHARED_IO_Q2_10_SEL 4 239 #define PINMUX_SHARED_IO_Q2_11_SEL 4 240 #define PINMUX_SHARED_IO_Q2_12_SEL 4 241 #define PINMUX_SHARED_IO_Q2_1_SEL 4 242 #define PINMUX_SHARED_IO_Q2_2_SEL 4 243 #define PINMUX_SHARED_IO_Q2_3_SEL 4 244 #define PINMUX_SHARED_IO_Q2_4_SEL 4 245 #define PINMUX_SHARED_IO_Q2_5_SEL 4 246 #define PINMUX_SHARED_IO_Q2_6_SEL 4 247 #define PINMUX_SHARED_IO_Q2_7_SEL 4 248 #define PINMUX_SHARED_IO_Q2_8_SEL 4 249 #define PINMUX_SHARED_IO_Q2_9_SEL 4 250 #define PINMUX_SHARED_IO_Q3_10_SEL 10 251 #define PINMUX_SHARED_IO_Q3_11_SEL 1 252 #define PINMUX_SHARED_IO_Q3_12_SEL 1 253 #define PINMUX_SHARED_IO_Q3_1_SEL 3 254 #define PINMUX_SHARED_IO_Q3_2_SEL 3 255 #define PINMUX_SHARED_IO_Q3_3_SEL 3 256 #define PINMUX_SHARED_IO_Q3_4_SEL 3 257 #define PINMUX_SHARED_IO_Q3_5_SEL 3 258 #define PINMUX_SHARED_IO_Q3_6_SEL 15 259 #define PINMUX_SHARED_IO_Q3_7_SEL 10 260 #define PINMUX_SHARED_IO_Q3_8_SEL 10 261 #define PINMUX_SHARED_IO_Q3_9_SEL 10 262 #define PINMUX_SHARED_IO_Q4_10_SEL 12 263 #define PINMUX_SHARED_IO_Q4_11_SEL 12 264 #define PINMUX_SHARED_IO_Q4_12_SEL 12 265 #define PINMUX_SHARED_IO_Q4_1_SEL 0 266 #define PINMUX_SHARED_IO_Q4_2_SEL 0 267 #define PINMUX_SHARED_IO_Q4_3_SEL 15 268 #define PINMUX_SHARED_IO_Q4_4_SEL 12 269 #define PINMUX_SHARED_IO_Q4_5_SEL 15 270 #define PINMUX_SHARED_IO_Q4_6_SEL 15 271 #define PINMUX_SHARED_IO_Q4_7_SEL 10 272 #define PINMUX_SHARED_IO_Q4_8_SEL 15 273 #define PINMUX_SHARED_IO_Q4_9_SEL 12 274 #define PINMUX_SPIM0_USEFPGA_SEL 0 275 #define PINMUX_SPIM1_USEFPGA_SEL 0 276 #define PINMUX_SPIS0_USEFPGA_SEL 0 277 #define PINMUX_SPIS1_USEFPGA_SEL 0 278 #define PINMUX_UART0_USEFPGA_SEL 0 279 #define PINMUX_UART1_USEFPGA_SEL 0 280 #define PINMUX_USB0_USEFPGA_SEL 0 281 #define PINMUX_USB1_USEFPGA_SEL 0 282 283 /* Bridge Configuration */ 284 #define F2H_AXI_SLAVE 1 285 #define F2SDRAM0_AXI_SLAVE 1 286 #define F2SDRAM1_AXI_SLAVE 0 287 #define F2SDRAM2_AXI_SLAVE 1 288 #define H2F_AXI_MASTER 1 289 #define LWH2F_AXI_MASTER 1 290 291 /* Voltage Select for Config IO */ 292 #define CONFIG_IO_BANK_VSEL \ 293 (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \ 294 (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3)) 295 296 /* Macro for Config IO bit mapping */ 297 #define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \ 298 ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \ 299 ((NAME ## _WK_PU_EN & 0x1) << 16) | \ 300 ((NAME ## _PU_SLW_RT & 0x1) << 13) | \ 301 ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \ 302 ((NAME ## _PD_SLW_RT & 0x1) << 5) | \ 303 (NAME ## _PD_DRV_STRG & 0x1f)) 304 305 #endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */ 306