1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright : STMicroelectronics 2018 4 */ 5 6/ { 7 aliases { 8 gpio0 = &gpioa; 9 gpio1 = &gpiob; 10 gpio2 = &gpioc; 11 gpio3 = &gpiod; 12 gpio4 = &gpioe; 13 gpio5 = &gpiof; 14 gpio6 = &gpiog; 15 gpio7 = &gpioh; 16 gpio8 = &gpioi; 17 gpio9 = &gpioj; 18 gpio10 = &gpiok; 19 gpio25 = &gpioz; 20 pinctrl0 = &pinctrl; 21 pinctrl1 = &pinctrl_z; 22 }; 23 24 clocks { 25 u-boot,dm-pre-reloc; 26 }; 27 28 /* need PSCI for sysreset during board_f */ 29 psci { 30 u-boot,dm-pre-proper; 31 }; 32 33 reboot { 34 u-boot,dm-pre-reloc; 35 compatible = "syscon-reboot"; 36 regmap = <&rcc>; 37 offset = <0x404>; 38 mask = <0x1>; 39 }; 40 41 soc { 42 u-boot,dm-pre-reloc; 43 44 ddr: ddr@5a003000 { 45 u-boot,dm-pre-reloc; 46 47 compatible = "st,stm32mp1-ddr"; 48 49 reg = <0x5A003000 0x550 50 0x5A004000 0x234>; 51 52 clocks = <&rcc AXIDCG>, 53 <&rcc DDRC1>, 54 <&rcc DDRC2>, 55 <&rcc DDRPHYC>, 56 <&rcc DDRCAPB>, 57 <&rcc DDRPHYCAPB>; 58 59 clock-names = "axidcg", 60 "ddrc1", 61 "ddrc2", 62 "ddrphyc", 63 "ddrcapb", 64 "ddrphycapb"; 65 66 status = "okay"; 67 }; 68 }; 69}; 70 71&bsec { 72 u-boot,dm-pre-reloc; 73}; 74 75&clk_csi { 76 u-boot,dm-pre-reloc; 77}; 78 79&clk_hsi { 80 u-boot,dm-pre-reloc; 81}; 82 83&clk_hse { 84 u-boot,dm-pre-reloc; 85}; 86 87&clk_lsi { 88 u-boot,dm-pre-reloc; 89}; 90 91&clk_lse { 92 u-boot,dm-pre-reloc; 93}; 94 95&cpu0_opp_table { 96 u-boot,dm-spl; 97 opp-650000000 { 98 u-boot,dm-spl; 99 }; 100 opp-800000000 { 101 u-boot,dm-spl; 102 }; 103}; 104 105&gpioa { 106 u-boot,dm-pre-reloc; 107}; 108 109&gpiob { 110 u-boot,dm-pre-reloc; 111}; 112 113&gpioc { 114 u-boot,dm-pre-reloc; 115}; 116 117&gpiod { 118 u-boot,dm-pre-reloc; 119}; 120 121&gpioe { 122 u-boot,dm-pre-reloc; 123}; 124 125&gpiof { 126 u-boot,dm-pre-reloc; 127}; 128 129&gpiog { 130 u-boot,dm-pre-reloc; 131}; 132 133&gpioh { 134 u-boot,dm-pre-reloc; 135}; 136 137&gpioi { 138 u-boot,dm-pre-reloc; 139}; 140 141&gpioj { 142 u-boot,dm-pre-reloc; 143}; 144 145&gpiok { 146 u-boot,dm-pre-reloc; 147}; 148 149&gpioz { 150 u-boot,dm-pre-reloc; 151}; 152 153&iwdg2 { 154 u-boot,dm-pre-reloc; 155}; 156 157/* pre-reloc probe = reserve video frame buffer in video_reserve() */ 158<dc { 159 u-boot,dm-pre-proper; 160}; 161 162/* temp = waiting kernel update */ 163&m4_rproc { 164 resets = <&rcc MCU_R>, 165 <&rcc MCU_HOLD_BOOT_R>; 166 reset-names = "mcu_rst", "hold_boot"; 167}; 168 169&pinctrl { 170 u-boot,dm-pre-reloc; 171}; 172 173&pinctrl_z { 174 u-boot,dm-pre-reloc; 175}; 176 177&pwr_regulators { 178 u-boot,dm-pre-reloc; 179}; 180 181&rcc { 182 u-boot,dm-pre-reloc; 183 #address-cells = <1>; 184 #size-cells = <0>; 185}; 186 187&sdmmc1 { 188 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 189}; 190 191&sdmmc2 { 192 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 193}; 194 195&sdmmc3 { 196 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 197}; 198 199&usart1 { 200 resets = <&rcc USART1_R>; 201}; 202 203&usart2 { 204 resets = <&rcc USART2_R>; 205}; 206 207&usart3 { 208 resets = <&rcc USART3_R>; 209}; 210 211&uart4 { 212 resets = <&rcc UART4_R>; 213}; 214 215&uart5 { 216 resets = <&rcc UART5_R>; 217}; 218 219&usart6 { 220 resets = <&rcc USART6_R>; 221}; 222 223&uart7 { 224 resets = <&rcc UART7_R>; 225}; 226 227&uart8{ 228 resets = <&rcc UART8_R>; 229}; 230 231