1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp15-u-boot.dtsi"
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11	aliases {
12		i2c3 = &i2c4;
13		mmc0 = &sdmmc1;
14		usb0 = &usbotg_hs;
15	};
16	config {
17		u-boot,boot-led = "heartbeat";
18		u-boot,error-led = "error";
19		u-boot,mmc-env-partition = "ssbl";
20		st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
21		st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
22		st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
23	};
24
25	firmware {
26		optee {
27			compatible = "linaro,optee-tz";
28			method = "smc";
29		};
30	};
31
32	reserved-memory {
33		optee@de000000 {
34			reg = <0xde000000 0x02000000>;
35			no-map;
36		};
37	};
38
39	led {
40		red {
41			label = "error";
42			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
43			default-state = "off";
44			status = "okay";
45		};
46	};
47};
48
49&adc {
50	status = "okay";
51};
52
53&clk_hse {
54	st,digbypass;
55};
56
57&i2c4 {
58	u-boot,dm-pre-reloc;
59};
60
61&i2c4_pins_a {
62	u-boot,dm-pre-reloc;
63	pins {
64		u-boot,dm-pre-reloc;
65	};
66};
67
68&pmic {
69	u-boot,dm-pre-reloc;
70};
71
72&rcc {
73	st,clksrc = <
74		CLK_MPU_PLL1P
75		CLK_AXI_PLL2P
76		CLK_MCU_PLL3P
77		CLK_PLL12_HSE
78		CLK_PLL3_HSE
79		CLK_PLL4_HSE
80		CLK_RTC_LSE
81		CLK_MCO1_DISABLED
82		CLK_MCO2_DISABLED
83	>;
84
85	st,clkdiv = <
86		1 /*MPU*/
87		0 /*AXI*/
88		0 /*MCU*/
89		1 /*APB1*/
90		1 /*APB2*/
91		1 /*APB3*/
92		1 /*APB4*/
93		2 /*APB5*/
94		23 /*RTC*/
95		0 /*MCO1*/
96		0 /*MCO2*/
97	>;
98
99	st,pkcs = <
100		CLK_CKPER_HSE
101		CLK_FMC_ACLK
102		CLK_QSPI_ACLK
103		CLK_ETH_DISABLED
104		CLK_SDMMC12_PLL4P
105		CLK_DSI_DSIPLL
106		CLK_STGEN_HSE
107		CLK_USBPHY_HSE
108		CLK_SPI2S1_PLL3Q
109		CLK_SPI2S23_PLL3Q
110		CLK_SPI45_HSI
111		CLK_SPI6_HSI
112		CLK_I2C46_HSI
113		CLK_SDMMC3_PLL4P
114		CLK_USBO_USBPHY
115		CLK_ADC_CKPER
116		CLK_CEC_LSE
117		CLK_I2C12_HSI
118		CLK_I2C35_HSI
119		CLK_UART1_HSI
120		CLK_UART24_HSI
121		CLK_UART35_HSI
122		CLK_UART6_HSI
123		CLK_UART78_HSI
124		CLK_SPDIF_PLL4P
125		CLK_FDCAN_PLL4R
126		CLK_SAI1_PLL3Q
127		CLK_SAI2_PLL3Q
128		CLK_SAI3_PLL3Q
129		CLK_SAI4_PLL3Q
130		CLK_RNG1_LSI
131		CLK_RNG2_LSI
132		CLK_LPTIM1_PCLK1
133		CLK_LPTIM23_PCLK3
134		CLK_LPTIM45_LSE
135	>;
136
137	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
138	pll2: st,pll@1 {
139		compatible = "st,stm32mp1-pll";
140		reg = <1>;
141		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
142		frac = < 0x1400 >;
143		u-boot,dm-pre-reloc;
144	};
145
146	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
147	pll3: st,pll@2 {
148		compatible = "st,stm32mp1-pll";
149		reg = <2>;
150		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
151		frac = < 0x1a04 >;
152		u-boot,dm-pre-reloc;
153	};
154
155	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
156	pll4: st,pll@3 {
157		compatible = "st,stm32mp1-pll";
158		reg = <3>;
159		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
160		u-boot,dm-pre-reloc;
161	};
162};
163
164&sdmmc1 {
165	u-boot,dm-spl;
166};
167
168&sdmmc1_b4_pins_a {
169	u-boot,dm-spl;
170	pins1 {
171		u-boot,dm-spl;
172	};
173	pins2 {
174		u-boot,dm-spl;
175	};
176};
177
178&uart4 {
179	u-boot,dm-pre-reloc;
180};
181
182&uart4_pins_a {
183	u-boot,dm-pre-reloc;
184	pins1 {
185		u-boot,dm-pre-reloc;
186	};
187	pins2 {
188		u-boot,dm-pre-reloc;
189		/* pull-up on rx to avoid floating level */
190		bias-pull-up;
191	};
192};
193
194&usbotg_hs {
195	u-boot,force-b-session-valid;
196};
197