1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal a2197 RevA System Controller on MGT 4 * 5 * (C) Copyright 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9/dts-v1/; 10 11#include "zynqmp.dtsi" 12#include "zynqmp-clk-ccf.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 model = "Versal System Controller on a2197 MGT Char board RevA"; 17 compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", 18 "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 19 20 aliases { 21 ethernet0 = &gem0; 22 gpio0 = &gpio; 23 i2c0 = &i2c0; 24 mmc0 = &sdhci0; 25 rtc0 = &rtc; 26 serial0 = &uart0; 27 serial1 = &dcc; 28 usb0 = &usb0; 29 }; 30 31 chosen { 32 bootargs = "earlycon"; 33 stdout-path = "serial0:115200n8"; 34 xlnx,eeprom = <&eeprom>; 35 }; 36 37 memory@0 { 38 device_type = "memory"; 39 reg = <0x0 0x0 0x0 0x80000000>; 40 }; 41 42 ina226-u74 { 43 compatible = "iio-hwmon"; 44 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 45 }; 46 ina226-u75 { 47 compatible = "iio-hwmon"; 48 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 49 }; 50 ina226-u78 { 51 compatible = "iio-hwmon"; 52 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 53 }; 54 ina226-u79 { 55 compatible = "iio-hwmon"; 56 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 57 }; 58 ina226-u82 { 59 compatible = "iio-hwmon"; 60 io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; 61 }; 62 ina226-u84 { 63 compatible = "iio-hwmon"; 64 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 65 }; 66}; 67 68&sdhci0 { /* emmc MIO 13-23 16GB */ 69 status = "okay"; 70 non-removable; 71 disable-wp; 72 bus-width = <8>; 73 xlnx,mio-bank = <0>; 74}; 75 76&uart0 { /* uart0 MIO38-39 */ 77 status = "okay"; 78 u-boot,dm-pre-reloc; 79}; 80 81&gem0 { /* eth MDIO 76/77 */ 82 status = "okay"; 83 phy-handle = <&phy0>; 84 phy-mode = "sgmii"; 85 is-internal-pcspma; 86 phy0: ethernet-phy@0 { /* marwell m88e1512 */ 87 reg = <0>; 88 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; 89/* xlnx,phy-type = <PHY_TYPE_SGMII>; */ 90 }; 91}; 92 93&gpio { 94 status = "okay"; 95 gpio-line-names = "", "", "", "", "", /* 0 - 4 */ 96 "", "", "", "", "", /* 5 - 9 */ 97 "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ 98 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ 99 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ 100 "", "", "", "", "", /* 25 - 29 */ 101 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ 102 "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ 103 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ 104 "", "", "", "", "", /* 45 - 49 */ 105 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ 106 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ 107 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ 108 "", "", "", "", "", /* 65 - 69 */ 109 "", "", "", "", "", /* 70 - 74 */ 110 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ 111 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ 112 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ 113 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ 114 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ 115 "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ 116 "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ 117 "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ 118 "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ 119 "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ 120 "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ 121 "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ 122 "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ 123 "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ 124 "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ 125 "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ 126 "", "", "", "", "", /* 150 - 154 */ 127 "", "", "", "", "", /* 155 - 159 */ 128 "", "", "", "", "", /* 160 - 164 */ 129 "", "", "", "", "", /* 165 - 169 */ 130 "", "", "", ""; /* 170 - 174 */ 131}; 132 133&i2c0 { /* MIO 34-35 - can't stay here */ 134 status = "okay"; 135 clock-frequency = <400000>; 136 scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; 137 sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; 138 i2c-mux@74 { /* u94 */ 139 compatible = "nxp,pca9548"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 reg = <0x74>; 143 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ 144 i2c@0 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 reg = <0>; 148 /* Use for storing information about SC board */ 149 eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ 150 compatible = "atmel,24c32"; 151 reg = <0x50>; 152 }; 153 }; 154 i2c@1 { /* CM_I2C_SCL - Samtec */ 155 #address-cells = <1>; 156 #size-cells = <0>; 157 reg = <1>; 158 }; 159 i2c@2 { /* PMBUS - AFX_PMBUS */ 160 #address-cells = <1>; 161 #size-cells = <0>; 162 reg = <2>; 163 tps544@d { /* u85 */ 164 compatible = "ti,tps544b25"; 165 reg = <0xd>; 166 }; 167 tps544@10 { /* u73 */ 168 compatible = "ti,tps544b25"; 169 reg = <0x10>; 170 }; 171 tps544@11 { /* u76 */ 172 compatible = "ti,tps544b25"; 173 reg = <0x11>; 174 }; 175 tps544@12 { /* u77 */ 176 compatible = "ti,tps544b25"; 177 reg = <0x12>; 178 }; 179 tps544@13 { /* u80 */ 180 compatible = "ti,tps544b25"; 181 reg = <0x13>; 182 }; 183 tps544@14 { /* u81 */ 184 compatible = "ti,tps544b25"; 185 reg = <0x14>; 186 }; 187 tps544@15 { /* u83 */ 188 compatible = "ti,tps544b25"; 189 reg = <0x15>; 190 }; 191 tps544@16 { /* u63 */ 192 compatible = "ti,tps544b25"; 193 reg = <0x16>; 194 }; 195 tps544@17 { /* u66 */ 196 compatible = "ti,tps544b25"; 197 reg = <0x17>; 198 }; 199 tps544@18 { /* u67 */ 200 compatible = "ti,tps544b25"; 201 reg = <0x18>; 202 }; 203 tps544@19 { /* u69 */ 204 compatible = "ti,tps544b25"; 205 reg = <0x19>; 206 }; 207 tps544@1d { /* u88 */ 208 compatible = "ti,tps544b25"; 209 reg = <0x1d>; 210 }; 211 tps544@1e { /* u89 */ 212 compatible = "ti,tps544b25"; 213 reg = <0x1e>; 214 }; 215 tps544@1f { /* u87 */ 216 compatible = "ti,tps544b25"; 217 reg = <0x1f>; 218 }; 219 tps544@20 { /* u71 */ 220 compatible = "ti,tps544b25"; 221 reg = <0x20>; 222 }; 223 u74: ina226@40 { /* u74 */ 224 compatible = "ti,ina226"; 225 #io-channel-cells = <1>; 226 label = "ina226-u74"; 227 reg = <0x40>; 228 shunt-resistor = <1000>; 229 }; 230 u75: ina226@41 { /* u75 */ 231 compatible = "ti,ina226"; 232 #io-channel-cells = <1>; 233 label = "ina226-u75"; 234 reg = <0x41>; 235 shunt-resistor = <1000>; 236 }; 237 u78: ina226@42 { /* u78 */ 238 compatible = "ti,ina226"; 239 #io-channel-cells = <1>; 240 label = "ina226-u78"; 241 reg = <0x42>; 242 shunt-resistor = <5000>; 243 }; 244 u79: ina226@43 { /* u79 */ 245 compatible = "ti,ina226"; 246 #io-channel-cells = <1>; 247 label = "ina226-u79"; 248 reg = <0x43>; 249 shunt-resistor = <1000>; 250 }; 251 u82: ina226@44 { /* u82 */ 252 compatible = "ti,ina226"; 253 #io-channel-cells = <1>; 254 label = "ina226-u82"; 255 reg = <0x44>; 256 shunt-resistor = <1000>; 257 }; 258 u84: ina226@45 { /* u84 */ 259 compatible = "ti,ina226"; 260 #io-channel-cells = <1>; 261 label = "ina226-u84"; 262 reg = <0x45>; 263 shunt-resistor = <5000>; 264 }; 265 tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ 266 compatible = "ti,tps53681", "ti,tps53679"; 267 reg = <0xc0>; 268 }; 269 }; 270 i2c@3 { /* fmc1 via JA2G */ 271 #address-cells = <1>; 272 #size-cells = <0>; 273 reg = <3>; 274 eeprom_fmc1: eeprom@50 { /* on FMC */ 275 compatible = "atmel,24c04"; 276 reg = <0x50>; 277 }; 278 }; 279 i2c@4 { /* fmc2 via JA3G */ 280 #address-cells = <1>; 281 #size-cells = <0>; 282 reg = <4>; 283 eeprom_fmc2: eeprom@50 { /* on FMC */ 284 compatible = "atmel,24c04"; 285 reg = <0x50>; 286 }; 287 }; 288 i2c@5 { /* fmc3 via JA4G */ 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <5>; 292 eeprom_fmc3: eeprom@50 { /* on FMC */ 293 compatible = "atmel,24c04"; 294 reg = <0x50>; 295 }; 296 }; 297 i2c@6 { /* ddr dimm */ 298 #address-cells = <1>; 299 #size-cells = <0>; 300 reg = <7>; 301 }; 302 /* 7 unused */ 303 }; 304}; 305 306&usb0 { /* USB0 MIO52-63 */ 307 status = "okay"; 308 xlnx,usb-polarity = <0>; 309 xlnx,usb-reset-mode = <0>; 310}; 311 312&dwc3_0 { 313 status = "okay"; 314 dr_mode = "peripheral"; 315 maximum-speed = "high-speed"; 316}; 317