1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Xilinx Versal a2197 RevA System Controller 4 * 5 * (C) Copyright 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9/dts-v1/; 10 11#include "zynqmp.dtsi" 12#include "zynqmp-clk-ccf.dtsi" 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 model = "Versal System Controller on a2197 Memory Char board RevA"; 17 compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", 18 "xlnx,zynqmp-a2197", "xlnx,zynqmp"; 19 20 aliases { 21 ethernet0 = &gem0; 22 gpio0 = &gpio; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 mmc0 = &sdhci0; 26 mmc1 = &sdhci1; 27 rtc0 = &rtc; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &dcc; 31 usb0 = &usb0; 32 usb1 = &usb1; 33 spi0 = &qspi; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 xlnx,eeprom = <&eeprom>; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */ 45 }; 46 47 ina226-vcc-aux { 48 compatible = "iio-hwmon"; 49 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; 50 }; 51 ina226-vcc-ram { 52 compatible = "iio-hwmon"; 53 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; 54 }; 55 ina226-vcc1v1-lp4 { 56 compatible = "iio-hwmon"; 57 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; 58 }; 59 ina226-vcc1v2-lp4 { 60 compatible = "iio-hwmon"; 61 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; 62 }; 63 ina226-vdd1-1v8-lp4 { 64 compatible = "iio-hwmon"; 65 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; 66 }; 67 ina226-vcc0v6-lp4 { 68 compatible = "iio-hwmon"; 69 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; 70 }; 71}; 72 73&qspi { 74 status = "okay"; 75 is-dual = <1>; 76 flash@0 { 77 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 78 #address-cells = <1>; 79 #size-cells = <1>; 80 reg = <0x0>; 81 spi-tx-bus-width = <1>; 82 spi-rx-bus-width = <4>; 83 spi-max-frequency = <108000000>; 84 }; 85}; 86 87&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ 88 status = "okay"; 89 non-removable; 90 disable-wp; 91 bus-width = <8>; 92 xlnx,mio-bank = <0>; /* FIXME tap delay */ 93}; 94 95&uart0 { /* uart0 MIO38-39 */ 96 status = "okay"; 97 u-boot,dm-pre-reloc; 98}; 99 100&uart1 { /* uart1 MIO40-41 */ 101 status = "okay"; 102 u-boot,dm-pre-reloc; 103}; 104 105&sdhci1 { /* sd1 MIO45-51 cd in place */ 106 status = "disable"; 107 no-1-8-v; 108 disable-wp; 109 xlnx,mio-bank = <1>; 110}; 111 112&gem0 { 113 status = "okay"; 114 phy-handle = <&phy0>; 115 phy-mode = "sgmii"; /* DTG generates this properly 1512 */ 116 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; 117 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ 118 reg = <0>; 119/* xlnx,phy-type = <PHY_TYPE_SGMII>; */ 120 }; 121}; 122 123&gpio { 124 status = "okay"; 125 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ 126 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ 127 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ 128 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ 129 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ 130 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ 131 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ 132 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ 133 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ 134 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ 135 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ 136 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ 137 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ 138 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ 139 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ 140 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ 141 "", "", "", "", "", /* 78 - 79 */ 142 "", "", "", "", "", /* 80 - 84 */ 143 "", "", "", "", "", /* 85 -89 */ 144 "", "", "", "", "", /* 90 - 94 */ 145 "", "", "", "", "", /* 95 - 99 */ 146 "", "", "", "", "", /* 100 - 104 */ 147 "", "", "", "", "", /* 105 - 109 */ 148 "", "", "", "", "", /* 110 - 114 */ 149 "", "", "", "", "", /* 115 - 119 */ 150 "", "", "", "", "", /* 120 - 124 */ 151 "", "", "", "", "", /* 125 - 129 */ 152 "", "", "", "", "", /* 130 - 134 */ 153 "", "", "", "", "", /* 135 - 139 */ 154 "", "", "", "", "", /* 140 - 144 */ 155 "", "", "", "", "", /* 145 - 149 */ 156 "", "", "", "", "", /* 150 - 154 */ 157 "", "", "", "", "", /* 155 - 159 */ 158 "", "", "", "", "", /* 160 - 164 */ 159 "", "", "", "", "", /* 165 - 169 */ 160 "", "", "", ""; /* 170 - 174 */ 161}; 162 163&i2c0 { /* MIO 34-35 - can't stay here */ 164 status = "okay"; 165 clock-frequency = <400000>; 166 i2c-mux@74 { /* u46 */ 167 compatible = "nxp,pca9548"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 reg = <0x74>; 171 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ 172 i2c@0 { /* PMBUS must be enabled via SW21 */ 173 #address-cells = <1>; 174 #size-cells = <0>; 175 reg = <0>; 176 reg_vcc1v2_lp4: tps544@15 { /* u97 */ 177 compatible = "ti,tps544b25"; 178 reg = <0x15>; 179 }; 180 reg_vcc1v1_lp4: tps544@16 { /* u95 */ 181 compatible = "ti,tps544b25"; 182 reg = <0x16>; 183 }; 184 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ 185 compatible = "ti,tps544b25"; 186 reg = <0x17>; 187 }; 188 /* UTIL_PMBUS connection */ 189 reg_vcc1v8: tps544@13 { /* u92 */ 190 compatible = "ti,tps544b25"; 191 reg = <0x13>; 192 }; 193 reg_vcc3v3: tps544@14 { /* u93 */ 194 compatible = "ti,tps544b25"; 195 reg = <0x14>; 196 }; 197 reg_vcc5v0: tps544@1e { /* u94 */ 198 compatible = "ti,tps544b25"; 199 reg = <0x1e>; 200 }; 201 }; 202 i2c@1 { /* PMBUS_INA226 */ 203 #address-cells = <1>; 204 #size-cells = <0>; 205 reg = <1>; 206 vcc_aux: ina226@42 { /* u86 */ 207 compatible = "ti,ina226"; 208 #io-channel-cells = <1>; 209 label = "ina226-vcc-aux"; 210 reg = <0x42>; 211 shunt-resistor = <5000>; 212 }; 213 vcc_ram: ina226@43 { /* u81 */ 214 compatible = "ti,ina226"; 215 #io-channel-cells = <1>; 216 label = "ina226-vcc-ram"; 217 reg = <0x43>; 218 shunt-resistor = <5000>; 219 }; 220 vcc1v1_lp4: ina226@46 { /* u96 */ 221 compatible = "ti,ina226"; 222 #io-channel-cells = <1>; 223 label = "ina226-vcc1v1-lp4"; 224 reg = <0x46>; 225 shunt-resistor = <5000>; 226 }; 227 vcc1v2_lp4: ina226@47 { /* u98 */ 228 compatible = "ti,ina226"; 229 #io-channel-cells = <1>; 230 label = "ina226-vcc1v2-lp4"; 231 reg = <0x47>; 232 shunt-resistor = <5000>; 233 }; 234 vdd1_1v8_lp4: ina226@48 { /* u100 */ 235 compatible = "ti,ina226"; 236 #io-channel-cells = <1>; 237 label = "ina226-vdd1-1v8-lp4"; 238 reg = <0x48>; 239 shunt-resistor = <5000>; 240 }; 241 vcc0v6_lp4: ina226@49 { /* u101 */ 242 compatible = "ti,ina226"; 243 #io-channel-cells = <1>; 244 label = "ina226-vcc0v6-lp4"; 245 reg = <0x49>; 246 shunt-resistor = <5000>; 247 }; 248 }; 249 i2c@2 { /* PMBUS1 */ 250 #address-cells = <1>; 251 #size-cells = <0>; 252 reg = <2>; 253 reg_vccint: tps53681@c0 { /* u69 */ 254 compatible = "ti,tps53681", "ti,tps53679"; 255 reg = <0xc0>; 256 }; 257 reg_vcc_pmc: tps544@7 { /* u80 */ 258 compatible = "ti,tps544b25"; 259 reg = <0x7>; 260 }; 261 reg_vcc_ram: tps544@8 { /* u82 */ 262 compatible = "ti,tps544b25"; 263 reg = <0x8>; 264 }; 265 reg_vcc_pslp: tps544@9 { /* u83 */ 266 compatible = "ti,tps544b25"; 267 reg = <0x9>; 268 }; 269 reg_vcc_psfp: tps544@a { /* u84 */ 270 compatible = "ti,tps544b25"; 271 reg = <0xa>; 272 }; 273 reg_vccaux: tps544@d { /* u85 */ 274 compatible = "ti,tps544b25"; 275 reg = <0xd>; 276 }; 277 reg_vccaux_pmc: tps544@e { /* u87 */ 278 compatible = "ti,tps544b25"; 279 reg = <0xe>; 280 }; 281 reg_vcco_500: tps544@f { /* u88 */ 282 compatible = "ti,tps544b25"; 283 reg = <0xf>; 284 }; 285 reg_vcco_501: tps544@10 { /* u89 */ 286 compatible = "ti,tps544b25"; 287 reg = <0x10>; 288 }; 289 reg_vcco_502: tps544@11 { /* u90 */ 290 compatible = "ti,tps544b25"; 291 reg = <0x11>; 292 }; 293 reg_vcco_503: tps544@12 { /* u91 */ 294 compatible = "ti,tps544b25"; 295 reg = <0x12>; 296 }; 297 }; 298 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ 299 #address-cells = <1>; 300 #size-cells = <0>; 301 /* reg = <3>; */ 302 }; 303 i2c@4 { /* LP_I2C_SM */ 304 #address-cells = <1>; 305 #size-cells = <0>; 306 reg = <4>; 307 /* connected to U20G */ 308 }; 309 /* 5-7 unused */ 310 }; 311}; 312 313/* TODO sysctrl via J239 */ 314/* TODO samtec J212G/H via J242 */ 315/* TODO teensy via U30 PCA9543A bus 1 */ 316&i2c1 { /* i2c1 MIO 36-37 */ 317 status = "okay"; 318 clock-frequency = <400000>; 319 320 /* Must be enabled via J242 */ 321 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ 322 compatible = "atmel,24c02"; 323 reg = <0x51>; 324 }; 325 326 i2c-mux@74 { /* u47 */ 327 compatible = "nxp,pca9548"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <0x74>; 331 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ 332 dc_i2c: i2c@0 { /* DC_I2C */ 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <0>; 336 /* Use for storing information about SC board */ 337 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ 338 compatible = "atmel,24c08"; 339 reg = <0x54>; 340 }; 341 si570_ref_clk: clock-generator@5d { /* u26 */ 342 #clock-cells = <0>; 343 compatible = "silabs,si570"; 344 reg = <0x5d>; /* FIXME addr */ 345 temperature-stability = <50>; 346 factory-fout = <33333333>; 347 clock-frequency = <33333333>; 348 clock-output-names = "REF_CLK"; /* FIXME */ 349 silabs,skip-recall; 350 }; 351 /* Connection via Samtec U20D */ 352 /* Use for storing information about X-PRC card */ 353 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ 354 compatible = "atmel,24c02"; 355 reg = <0x52>; 356 }; 357 358 /* Use for setting up certain features on X-PRC card */ 359 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ 360 compatible = "nxp,pca9534"; 361 reg = <0x22>; 362 gpio-controller; /* IRQ not connected */ 363 #gpio-cells = <2>; 364 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", 365 "", "", "", ""; 366 gtr_sel0 { 367 gpio-hog; 368 gpios = <0 0>; 369 input; /* FIXME add meaning */ 370 line-name = "sw4_1"; 371 }; 372 gtr_sel1 { 373 gpio-hog; 374 gpios = <1 0>; 375 input; /* FIXME add meaning */ 376 line-name = "sw4_2"; 377 }; 378 gtr_sel2 { 379 gpio-hog; 380 gpios = <2 0>; 381 input; /* FIXME add meaning */ 382 line-name = "sw4_3"; 383 }; 384 gtr_sel3 { 385 gpio-hog; 386 gpios = <3 0>; 387 input; /* FIXME add meaning */ 388 line-name = "sw4_4"; 389 }; 390 }; 391 }; 392 i2c@2 { /* C0_LP4 */ 393 #address-cells = <1>; 394 #size-cells = <0>; 395 reg = <2>; 396 si570_c0_lp4: clock-generator@55 { /* u10 */ 397 #clock-cells = <0>; 398 compatible = "silabs,si570"; 399 reg = <0x55>; 400 temperature-stability = <50>; 401 factory-fout = <30000000>; 402 clock-frequency = <30000000>; 403 clock-output-names = "C0_LP4_SI570_CLK"; 404 }; 405 }; 406 i2c@3 { /* C1_LP4 */ 407 #address-cells = <1>; 408 #size-cells = <0>; 409 reg = <3>; 410 si570_c1_lp4: clock-generator@5d { /* u10 */ 411 #clock-cells = <0>; 412 compatible = "silabs,si570"; 413 reg = <0x5d>; /* FIXME addr */ 414 temperature-stability = <50>; 415 factory-fout = <30000000>; 416 clock-frequency = <30000000>; 417 clock-output-names = "C1_LP4_SI570_CLK"; 418 }; 419 }; 420 i2c@4 { /* C2_LP4 */ 421 #address-cells = <1>; 422 #size-cells = <0>; 423 reg = <4>; 424 si570_c2_lp4: clock-generator@55 { /* u10 */ 425 #clock-cells = <0>; 426 compatible = "silabs,si570"; 427 reg = <0x55>; 428 temperature-stability = <50>; 429 factory-fout = <30000000>; 430 clock-frequency = <30000000>; 431 clock-output-names = "C2_LP4_SI570_CLK"; 432 }; 433 }; 434 i2c@5 { /* C3_LP4 */ 435 #address-cells = <1>; 436 #size-cells = <0>; 437 reg = <5>; 438 si570_c3_lp4: clock-generator@55 { /* u15 */ 439 #clock-cells = <0>; 440 compatible = "silabs,si570"; 441 reg = <0x55>; 442 temperature-stability = <50>; 443 factory-fout = <30000000>; 444 clock-frequency = <30000000>; 445 clock-output-names = "C3_LP4_SI570_CLK"; 446 }; 447 }; 448 i2c@6 { /* HSDP_SI570 */ 449 #address-cells = <1>; 450 #size-cells = <0>; 451 reg = <6>; 452 si570_hsdp: clock-generator@5d { /* u19 */ 453 #clock-cells = <0>; 454 compatible = "silabs,si570"; 455 reg = <0x5d>; /* FIXME addr */ 456 temperature-stability = <50>; 457 factory-fout = <156250000>; 458 clock-frequency = <156250000>; 459 clock-output-names = "HSDP_SI570"; 460 }; 461 }; 462 }; 463}; 464 465&usb0 { 466 status = "okay"; 467 xlnx,usb-polarity = <0>; 468 xlnx,usb-reset-mode = <0>; 469}; 470 471&dwc3_0 { 472 status = "okay"; 473 dr_mode = "host"; 474 /* dr_mode = "peripheral"; */ 475 maximum-speed = "high-speed"; 476}; 477 478&usb1 { 479 status = "disabled"; /* not at mem board */ 480 xlnx,usb-polarity = <0>; 481 xlnx,usb-reset-mode = <0>; 482}; 483 484&dwc3_1 { 485 /delete-property/ phy-names ; 486 /delete-property/ phys ; 487 maximum-speed = "high-speed"; 488 snps,dis_u2_susphy_quirk ; 489 snps,dis_u3_susphy_quirk ; 490 status = "disabled"; 491}; 492