1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP Mini Configuration
4 *
5 * (C) Copyright 2015 - 2020, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13/ {
14	model = "ZynqMP MINI QSPI";
15	compatible = "xlnx,zynqmp";
16	#address-cells = <2>;
17	#size-cells = <1>;
18
19	aliases {
20		serial0 = &dcc;
21		spi0 = &qspi;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@fffc0000 {
29		device_type = "memory";
30		reg = <0x0 0xfffc0000 0x40000>;
31	};
32
33	dcc: dcc {
34		compatible = "arm,dcc";
35		status = "disabled";
36		u-boot,dm-pre-reloc;
37	};
38
39	amba: amba {
40		compatible = "simple-bus";
41		#address-cells = <2>;
42		#size-cells = <1>;
43		ranges;
44
45		qspi: spi@ff0f0000 {
46			compatible = "xlnx,zynqmp-qspi-1.0";
47			status = "disabled";
48			clock-names = "ref_clk", "pclk";
49			clocks = <&misc_clk &misc_clk>;
50			num-cs = <1>;
51			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
52			#address-cells = <1>;
53			#size-cells = <0>;
54		};
55
56		misc_clk: misc_clk {
57			compatible = "fixed-clock";
58			#clock-cells = <0>;
59			clock-frequency = <125000000>;
60		};
61	};
62};
63
64&qspi {
65	status = "okay";
66	flash0: flash@0 {
67		compatible = "n25q512a11", "jedec,spi-nor";
68		#address-cells = <1>;
69		#size-cells = <1>;
70		reg = <0x0>;
71		spi-tx-bus-width = <1>;
72		spi-rx-bus-width = <4>;
73		spi-max-frequency = <40000000>;
74	};
75};
76
77&dcc {
78	status = "okay";
79};
80