1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
4 *
5 * (C) Copyright 2015 - 2020, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/phy/phy.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17
18/ {
19	model = "ZynqMP zc1751-xm015-dc1 RevA";
20	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		gpio0 = &gpio;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci0;
27		mmc1 = &sdhci1;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		spi0 = &qspi;
31		usb0 = &usb0;
32	};
33
34	chosen {
35		bootargs = "earlycon";
36		stdout-path = "serial0:115200n8";
37	};
38
39	memory@0 {
40		device_type = "memory";
41		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
42	};
43
44	clock_si5338_0: clk27 {	/* u55 SI5338-GM */
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <27000000>;
48	};
49
50	clock_si5338_2: clk26 {
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <26000000>;
54	};
55
56	clock_si5338_3: clk150 {
57		compatible = "fixed-clock";
58		#clock-cells = <0>;
59		clock-frequency = <150000000>;
60	};
61};
62
63&psgtr {
64	status = "okay";
65	/* dp, usb3, sata */
66	clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
67	clock-names = "ref1", "ref2", "ref3";
68};
69
70&fpd_dma_chan1 {
71	status = "okay";
72};
73
74&fpd_dma_chan2 {
75	status = "okay";
76};
77
78&fpd_dma_chan3 {
79	status = "okay";
80};
81
82&fpd_dma_chan4 {
83	status = "okay";
84};
85
86&fpd_dma_chan5 {
87	status = "okay";
88};
89
90&fpd_dma_chan6 {
91	status = "okay";
92};
93
94&fpd_dma_chan7 {
95	status = "okay";
96};
97
98&fpd_dma_chan8 {
99	status = "okay";
100};
101
102&gem3 {
103	status = "okay";
104	phy-handle = <&phy0>;
105	phy-mode = "rgmii-id";
106	pinctrl-names = "default";
107	pinctrl-0 = <&pinctrl_gem3_default>;
108	phy0: ethernet-phy@0 {
109		reg = <0>;
110	};
111};
112
113&gpio {
114	status = "okay";
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_gpio_default>;
117};
118
119&gpu {
120	status = "okay";
121};
122
123&i2c1 {
124	status = "okay";
125	clock-frequency = <400000>;
126	pinctrl-names = "default", "gpio";
127	pinctrl-0 = <&pinctrl_i2c1_default>;
128	pinctrl-1 = <&pinctrl_i2c1_gpio>;
129	scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
130	sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
131
132	eeprom: eeprom@55 {
133		compatible = "atmel,24c64"; /* 24AA64 */
134		reg = <0x55>;
135	};
136};
137
138&pinctrl0 {
139	status = "okay";
140	pinctrl_i2c1_default: i2c1-default {
141		mux {
142			groups = "i2c1_9_grp";
143			function = "i2c1";
144		};
145
146		conf {
147			groups = "i2c1_9_grp";
148			bias-pull-up;
149			slew-rate = <SLEW_RATE_SLOW>;
150			power-source = <IO_STANDARD_LVCMOS18>;
151		};
152	};
153
154	pinctrl_i2c1_gpio: i2c1-gpio {
155		mux {
156			groups = "gpio0_36_grp", "gpio0_37_grp";
157			function = "gpio0";
158		};
159
160		conf {
161			groups = "gpio0_36_grp", "gpio0_37_grp";
162			slew-rate = <SLEW_RATE_SLOW>;
163			power-source = <IO_STANDARD_LVCMOS18>;
164		};
165	};
166
167	pinctrl_uart0_default: uart0-default {
168		mux {
169			groups = "uart0_8_grp";
170			function = "uart0";
171		};
172
173		conf {
174			groups = "uart0_8_grp";
175			slew-rate = <SLEW_RATE_SLOW>;
176			power-source = <IO_STANDARD_LVCMOS18>;
177		};
178
179		conf-rx {
180			pins = "MIO34";
181			bias-high-impedance;
182		};
183
184		conf-tx {
185			pins = "MIO35";
186			bias-disable;
187		};
188	};
189
190	pinctrl_usb0_default: usb0-default {
191		mux {
192			groups = "usb0_0_grp";
193			function = "usb0";
194		};
195
196		conf {
197			groups = "usb0_0_grp";
198			slew-rate = <SLEW_RATE_SLOW>;
199			power-source = <IO_STANDARD_LVCMOS18>;
200		};
201
202		conf-rx {
203			pins = "MIO52", "MIO53", "MIO55";
204			bias-high-impedance;
205		};
206
207		conf-tx {
208			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
209			       "MIO60", "MIO61", "MIO62", "MIO63";
210			bias-disable;
211		};
212	};
213
214	pinctrl_gem3_default: gem3-default {
215		mux {
216			function = "ethernet3";
217			groups = "ethernet3_0_grp";
218		};
219
220		conf {
221			groups = "ethernet3_0_grp";
222			slew-rate = <SLEW_RATE_SLOW>;
223			power-source = <IO_STANDARD_LVCMOS18>;
224		};
225
226		conf-rx {
227			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
228									"MIO75";
229			bias-high-impedance;
230			low-power-disable;
231		};
232
233		conf-tx {
234			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
235									"MIO69";
236			bias-disable;
237			low-power-enable;
238		};
239
240		mux-mdio {
241			function = "mdio3";
242			groups = "mdio3_0_grp";
243		};
244
245		conf-mdio {
246			groups = "mdio3_0_grp";
247			slew-rate = <SLEW_RATE_SLOW>;
248			power-source = <IO_STANDARD_LVCMOS18>;
249			bias-disable;
250		};
251	};
252
253	pinctrl_sdhci0_default: sdhci0-default {
254		mux {
255			groups = "sdio0_0_grp";
256			function = "sdio0";
257		};
258
259		conf {
260			groups = "sdio0_0_grp";
261			slew-rate = <SLEW_RATE_SLOW>;
262			power-source = <IO_STANDARD_LVCMOS18>;
263			bias-disable;
264		};
265
266		mux-cd {
267			groups = "sdio0_cd_0_grp";
268			function = "sdio0_cd";
269		};
270
271		conf-cd {
272			groups = "sdio0_cd_0_grp";
273			bias-high-impedance;
274			bias-pull-up;
275			slew-rate = <SLEW_RATE_SLOW>;
276			power-source = <IO_STANDARD_LVCMOS18>;
277		};
278
279		mux-wp {
280			groups = "sdio0_wp_0_grp";
281			function = "sdio0_wp";
282		};
283
284		conf-wp {
285			groups = "sdio0_wp_0_grp";
286			bias-high-impedance;
287			bias-pull-up;
288			slew-rate = <SLEW_RATE_SLOW>;
289			power-source = <IO_STANDARD_LVCMOS18>;
290		};
291	};
292
293	pinctrl_sdhci1_default: sdhci1-default {
294		mux {
295			groups = "sdio1_0_grp";
296			function = "sdio1";
297		};
298
299		conf {
300			groups = "sdio1_0_grp";
301			slew-rate = <SLEW_RATE_SLOW>;
302			power-source = <IO_STANDARD_LVCMOS18>;
303			bias-disable;
304		};
305
306		mux-cd {
307			groups = "sdio1_cd_0_grp";
308			function = "sdio1_cd";
309		};
310
311		conf-cd {
312			groups = "sdio1_cd_0_grp";
313			bias-high-impedance;
314			bias-pull-up;
315			slew-rate = <SLEW_RATE_SLOW>;
316			power-source = <IO_STANDARD_LVCMOS18>;
317		};
318
319		mux-wp {
320			groups = "sdio1_wp_0_grp";
321			function = "sdio1_wp";
322		};
323
324		conf-wp {
325			groups = "sdio1_wp_0_grp";
326			bias-high-impedance;
327			bias-pull-up;
328			slew-rate = <SLEW_RATE_SLOW>;
329			power-source = <IO_STANDARD_LVCMOS18>;
330		};
331	};
332
333	pinctrl_gpio_default: gpio-default {
334		mux {
335			function = "gpio0";
336			groups = "gpio0_38_grp";
337		};
338
339		conf {
340			groups = "gpio0_38_grp";
341			bias-disable;
342			slew-rate = <SLEW_RATE_SLOW>;
343			power-source = <IO_STANDARD_LVCMOS18>;
344		};
345	};
346};
347
348&qspi {
349	status = "okay";
350	flash@0 {
351		compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
352		#address-cells = <1>;
353		#size-cells = <1>;
354		reg = <0x0>;
355		spi-tx-bus-width = <1>;
356		spi-rx-bus-width = <4>;
357		spi-max-frequency = <108000000>; /* Based on DC1 spec */
358		partition@0 { /* for testing purpose */
359			label = "qspi-fsbl-uboot";
360			reg = <0x0 0x100000>;
361		};
362		partition@100000 { /* for testing purpose */
363			label = "qspi-linux";
364			reg = <0x100000 0x500000>;
365		};
366		partition@600000 { /* for testing purpose */
367			label = "qspi-device-tree";
368			reg = <0x600000 0x20000>;
369		};
370		partition@620000 { /* for testing purpose */
371			label = "qspi-rootfs";
372			reg = <0x620000 0x5E0000>;
373		};
374	};
375};
376
377&rtc {
378	status = "okay";
379};
380
381&sata {
382	status = "okay";
383	/* SATA phy OOB timing settings */
384	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
385	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
386	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
387	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
388	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
389	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
390	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
391	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
392	phy-names = "sata-phy";
393	phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
394};
395
396/* eMMC */
397&sdhci0 {
398	status = "okay";
399	pinctrl-names = "default";
400	pinctrl-0 = <&pinctrl_sdhci0_default>;
401	bus-width = <8>;
402	xlnx,mio-bank = <0>;
403};
404
405/* SD1 with level shifter */
406&sdhci1 {
407	status = "okay";
408	/*
409	 * This property should be removed for supporting UHS mode
410	 */
411	no-1-8-v;
412	pinctrl-names = "default";
413	pinctrl-0 = <&pinctrl_sdhci1_default>;
414	xlnx,mio-bank = <1>;
415};
416
417&uart0 {
418	status = "okay";
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_uart0_default>;
421};
422
423/* ULPI SMSC USB3320 */
424&usb0 {
425	status = "okay";
426	pinctrl-names = "default";
427	pinctrl-0 = <&pinctrl_usb0_default>;
428};
429
430&dwc3_0 {
431	status = "okay";
432	dr_mode = "host";
433	snps,usb3_lpm_capable;
434	phy-names = "usb3-phy";
435	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
436};
437
438&zynqmp_dpdma {
439	status = "okay";
440};
441
442&zynqmp_dpsub {
443	status = "okay";
444};
445
446