1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU102 RevA 4 * 5 * (C) Copyright 2015 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU102 RevA"; 21 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 gpio0 = &gpio; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &dcc; 33 spi0 = &qspi; 34 usb0 = &usb0; 35 }; 36 37 chosen { 38 bootargs = "earlycon"; 39 stdout-path = "serial0:115200n8"; 40 xlnx,eeprom = &eeprom; 41 }; 42 43 memory@0 { 44 device_type = "memory"; 45 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 autorepeat; 51 sw19 { 52 label = "sw19"; 53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 54 linux,code = <KEY_DOWN>; 55 wakeup-source; 56 autorepeat; 57 }; 58 }; 59 60 leds { 61 compatible = "gpio-leds"; 62 heartbeat-led { 63 label = "heartbeat"; 64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 65 linux,default-trigger = "heartbeat"; 66 }; 67 }; 68 69 ina226-u76 { 70 compatible = "iio-hwmon"; 71 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; 72 }; 73 ina226-u77 { 74 compatible = "iio-hwmon"; 75 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 76 }; 77 ina226-u78 { 78 compatible = "iio-hwmon"; 79 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; 80 }; 81 ina226-u87 { 82 compatible = "iio-hwmon"; 83 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; 84 }; 85 ina226-u85 { 86 compatible = "iio-hwmon"; 87 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; 88 }; 89 ina226-u86 { 90 compatible = "iio-hwmon"; 91 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; 92 }; 93 ina226-u93 { 94 compatible = "iio-hwmon"; 95 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; 96 }; 97 ina226-u88 { 98 compatible = "iio-hwmon"; 99 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; 100 }; 101 ina226-u15 { 102 compatible = "iio-hwmon"; 103 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; 104 }; 105 ina226-u92 { 106 compatible = "iio-hwmon"; 107 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; 108 }; 109 ina226-u79 { 110 compatible = "iio-hwmon"; 111 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 112 }; 113 ina226-u81 { 114 compatible = "iio-hwmon"; 115 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; 116 }; 117 ina226-u80 { 118 compatible = "iio-hwmon"; 119 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; 120 }; 121 ina226-u84 { 122 compatible = "iio-hwmon"; 123 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; 124 }; 125 ina226-u16 { 126 compatible = "iio-hwmon"; 127 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; 128 }; 129 ina226-u65 { 130 compatible = "iio-hwmon"; 131 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 132 }; 133 ina226-u74 { 134 compatible = "iio-hwmon"; 135 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; 136 }; 137 ina226-u75 { 138 compatible = "iio-hwmon"; 139 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; 140 }; 141 142 /* 48MHz reference crystal */ 143 ref48: ref48M { 144 compatible = "fixed-clock"; 145 #clock-cells = <0>; 146 clock-frequency = <48000000>; 147 }; 148 149 refhdmi: refhdmi { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 clock-frequency = <114285000>; 153 }; 154}; 155 156&can1 { 157 status = "okay"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_can1_default>; 160}; 161 162&dcc { 163 status = "okay"; 164}; 165 166&fpd_dma_chan1 { 167 status = "okay"; 168}; 169 170&fpd_dma_chan2 { 171 status = "okay"; 172}; 173 174&fpd_dma_chan3 { 175 status = "okay"; 176}; 177 178&fpd_dma_chan4 { 179 status = "okay"; 180}; 181 182&fpd_dma_chan5 { 183 status = "okay"; 184}; 185 186&fpd_dma_chan6 { 187 status = "okay"; 188}; 189 190&fpd_dma_chan7 { 191 status = "okay"; 192}; 193 194&fpd_dma_chan8 { 195 status = "okay"; 196}; 197 198&gem3 { 199 status = "okay"; 200 phy-handle = <&phy0>; 201 phy-mode = "rgmii-id"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_gem3_default>; 204 phy0: ethernet-phy@21 { 205 reg = <21>; 206 ti,rx-internal-delay = <0x8>; 207 ti,tx-internal-delay = <0xa>; 208 ti,fifo-depth = <0x1>; 209 ti,dp83867-rxctrl-strap-quirk; 210 /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ 211 }; 212}; 213 214&gpio { 215 status = "okay"; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_gpio_default>; 218}; 219 220&gpu { 221 status = "okay"; 222}; 223 224&i2c0 { 225 status = "okay"; 226 clock-frequency = <400000>; 227 pinctrl-names = "default", "gpio"; 228 pinctrl-0 = <&pinctrl_i2c0_default>; 229 pinctrl-1 = <&pinctrl_i2c0_gpio>; 230 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 231 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 232 233 tca6416_u97: gpio@20 { 234 compatible = "ti,tca6416"; 235 reg = <0x20>; 236 gpio-controller; /* IRQ not connected */ 237 #gpio-cells = <2>; 238 gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", 239 "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", 240 "", "", "", "", "", "", "", "", ""; 241 gtr-sel0-hog { 242 gpio-hog; 243 gpios = <0 0>; 244 output-low; /* PCIE = 0, DP = 1 */ 245 line-name = "sel0"; 246 }; 247 gtr-sel1-hog { 248 gpio-hog; 249 gpios = <1 0>; 250 output-high; /* PCIE = 0, DP = 1 */ 251 line-name = "sel1"; 252 }; 253 gtr-sel2-hog { 254 gpio-hog; 255 gpios = <2 0>; 256 output-high; /* PCIE = 0, USB0 = 1 */ 257 line-name = "sel2"; 258 }; 259 gtr-sel3-hog { 260 gpio-hog; 261 gpios = <3 0>; 262 output-high; /* PCIE = 0, SATA = 1 */ 263 line-name = "sel3"; 264 }; 265 }; 266 267 tca6416_u61: gpio@21 { 268 compatible = "ti,tca6416"; 269 reg = <0x21>; 270 gpio-controller; /* IRQ not connected */ 271 #gpio-cells = <2>; 272 gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", 273 "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", 274 "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", 275 "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; 276 }; 277 278 i2c-mux@75 { /* u60 */ 279 compatible = "nxp,pca9544"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 reg = <0x75>; 283 i2c@0 { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 reg = <0>; 287 /* PS_PMBUS */ 288 u76: ina226@40 { /* u76 */ 289 compatible = "ti,ina226"; 290 #io-channel-cells = <1>; 291 label = "ina226-u76"; 292 reg = <0x40>; 293 shunt-resistor = <5000>; 294 }; 295 u77: ina226@41 { /* u77 */ 296 compatible = "ti,ina226"; 297 #io-channel-cells = <1>; 298 label = "ina226-u77"; 299 reg = <0x41>; 300 shunt-resistor = <5000>; 301 }; 302 u78: ina226@42 { /* u78 */ 303 compatible = "ti,ina226"; 304 #io-channel-cells = <1>; 305 label = "ina226-u78"; 306 reg = <0x42>; 307 shunt-resistor = <5000>; 308 }; 309 u87: ina226@43 { /* u87 */ 310 compatible = "ti,ina226"; 311 #io-channel-cells = <1>; 312 label = "ina226-u87"; 313 reg = <0x43>; 314 shunt-resistor = <5000>; 315 }; 316 u85: ina226@44 { /* u85 */ 317 compatible = "ti,ina226"; 318 #io-channel-cells = <1>; 319 label = "ina226-u85"; 320 reg = <0x44>; 321 shunt-resistor = <5000>; 322 }; 323 u86: ina226@45 { /* u86 */ 324 compatible = "ti,ina226"; 325 #io-channel-cells = <1>; 326 label = "ina226-u86"; 327 reg = <0x45>; 328 shunt-resistor = <5000>; 329 }; 330 u93: ina226@46 { /* u93 */ 331 compatible = "ti,ina226"; 332 #io-channel-cells = <1>; 333 label = "ina226-u93"; 334 reg = <0x46>; 335 shunt-resistor = <5000>; 336 }; 337 u88: ina226@47 { /* u88 */ 338 compatible = "ti,ina226"; 339 #io-channel-cells = <1>; 340 label = "ina226-u88"; 341 reg = <0x47>; 342 shunt-resistor = <5000>; 343 }; 344 u15: ina226@4a { /* u15 */ 345 compatible = "ti,ina226"; 346 #io-channel-cells = <1>; 347 label = "ina226-u15"; 348 reg = <0x4a>; 349 shunt-resistor = <5000>; 350 }; 351 u92: ina226@4b { /* u92 */ 352 compatible = "ti,ina226"; 353 #io-channel-cells = <1>; 354 label = "ina226-u92"; 355 reg = <0x4b>; 356 shunt-resistor = <5000>; 357 }; 358 }; 359 i2c@1 { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <1>; 363 /* PL_PMBUS */ 364 u79: ina226@40 { /* u79 */ 365 compatible = "ti,ina226"; 366 #io-channel-cells = <1>; 367 label = "ina226-u79"; 368 reg = <0x40>; 369 shunt-resistor = <2000>; 370 }; 371 u81: ina226@41 { /* u81 */ 372 compatible = "ti,ina226"; 373 #io-channel-cells = <1>; 374 label = "ina226-u81"; 375 reg = <0x41>; 376 shunt-resistor = <5000>; 377 }; 378 u80: ina226@42 { /* u80 */ 379 compatible = "ti,ina226"; 380 #io-channel-cells = <1>; 381 label = "ina226-u80"; 382 reg = <0x42>; 383 shunt-resistor = <5000>; 384 }; 385 u84: ina226@43 { /* u84 */ 386 compatible = "ti,ina226"; 387 #io-channel-cells = <1>; 388 label = "ina226-u84"; 389 reg = <0x43>; 390 shunt-resistor = <5000>; 391 }; 392 u16: ina226@44 { /* u16 */ 393 compatible = "ti,ina226"; 394 #io-channel-cells = <1>; 395 label = "ina226-u16"; 396 reg = <0x44>; 397 shunt-resistor = <5000>; 398 }; 399 u65: ina226@45 { /* u65 */ 400 compatible = "ti,ina226"; 401 #io-channel-cells = <1>; 402 label = "ina226-u65"; 403 reg = <0x45>; 404 shunt-resistor = <5000>; 405 }; 406 u74: ina226@46 { /* u74 */ 407 compatible = "ti,ina226"; 408 #io-channel-cells = <1>; 409 label = "ina226-u74"; 410 reg = <0x46>; 411 shunt-resistor = <5000>; 412 }; 413 u75: ina226@47 { /* u75 */ 414 compatible = "ti,ina226"; 415 #io-channel-cells = <1>; 416 label = "ina226-u75"; 417 reg = <0x47>; 418 shunt-resistor = <5000>; 419 }; 420 }; 421 i2c@2 { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 reg = <2>; 425 /* MAXIM_PMBUS - 00 */ 426 max15301@a { /* u46 */ 427 compatible = "maxim,max15301"; 428 reg = <0xa>; 429 }; 430 max15303@b { /* u4 */ 431 compatible = "maxim,max15303"; 432 reg = <0xb>; 433 }; 434 max15303@10 { /* u13 */ 435 compatible = "maxim,max15303"; 436 reg = <0x10>; 437 }; 438 max15301@13 { /* u47 */ 439 compatible = "maxim,max15301"; 440 reg = <0x13>; 441 }; 442 max15303@14 { /* u7 */ 443 compatible = "maxim,max15303"; 444 reg = <0x14>; 445 }; 446 max15303@15 { /* u6 */ 447 compatible = "maxim,max15303"; 448 reg = <0x15>; 449 }; 450 max15303@16 { /* u10 */ 451 compatible = "maxim,max15303"; 452 reg = <0x16>; 453 }; 454 max15303@17 { /* u9 */ 455 compatible = "maxim,max15303"; 456 reg = <0x17>; 457 }; 458 max15301@18 { /* u63 */ 459 compatible = "maxim,max15301"; 460 reg = <0x18>; 461 }; 462 max15303@1a { /* u49 */ 463 compatible = "maxim,max15303"; 464 reg = <0x1a>; 465 }; 466 max15303@1d { /* u18 */ 467 compatible = "maxim,max15303"; 468 reg = <0x1d>; 469 }; 470 max15303@20 { /* u8 */ 471 compatible = "maxim,max15303"; 472 status = "disabled"; /* unreachable */ 473 reg = <0x20>; 474 }; 475 max20751@72 { /* u95 */ 476 compatible = "maxim,max20751"; 477 reg = <0x72>; 478 }; 479 max20751@73 { /* u96 */ 480 compatible = "maxim,max20751"; 481 reg = <0x73>; 482 }; 483 }; 484 /* Bus 3 is not connected */ 485 }; 486}; 487 488&i2c1 { 489 status = "okay"; 490 clock-frequency = <400000>; 491 pinctrl-names = "default", "gpio"; 492 pinctrl-0 = <&pinctrl_i2c1_default>; 493 pinctrl-1 = <&pinctrl_i2c1_gpio>; 494 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 495 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 496 497 /* PL i2c via PCA9306 - u45 */ 498 i2c-mux@74 { /* u34 */ 499 compatible = "nxp,pca9548"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <0x74>; 503 i2c@0 { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0>; 507 /* 508 * IIC_EEPROM 1kB memory which uses 256B blocks 509 * where every block has different address. 510 * 0 - 256B address 0x54 511 * 256B - 512B address 0x55 512 * 512B - 768B address 0x56 513 * 768B - 1024B address 0x57 514 */ 515 eeprom: eeprom@54 { /* u23 */ 516 compatible = "atmel,24c08"; 517 reg = <0x54>; 518 }; 519 }; 520 i2c@1 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 reg = <1>; 524 si5341: clock-generator@36 { /* SI5341 - u69 */ 525 compatible = "silabs,si5341"; 526 reg = <0x36>; 527 #clock-cells = <2>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&ref48>; 531 clock-names = "xtal"; 532 clock-output-names = "si5341"; 533 534 si5341_0: out@0 { 535 /* refclk0 for PS-GT, used for DP */ 536 reg = <0>; 537 always-on; 538 }; 539 si5341_2: out@2 { 540 /* refclk2 for PS-GT, used for USB3 */ 541 reg = <2>; 542 always-on; 543 }; 544 si5341_3: out@3 { 545 /* refclk3 for PS-GT, used for SATA */ 546 reg = <3>; 547 always-on; 548 }; 549 si5341_4: out@4 { 550 /* refclk4 for PS-GT, used for PCIE slot */ 551 reg = <4>; 552 always-on; 553 }; 554 si5341_5: out@5 { 555 /* refclk5 for PS-GT, used for PCIE */ 556 reg = <5>; 557 always-on; 558 }; 559 si5341_6: out@6 { 560 /* refclk6 PL CLK125 */ 561 reg = <6>; 562 always-on; 563 }; 564 si5341_7: out@7 { 565 /* refclk7 PL CLK74 */ 566 reg = <7>; 567 always-on; 568 }; 569 si5341_9: out@9 { 570 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 571 reg = <9>; 572 always-on; 573 }; 574 }; 575 }; 576 i2c@2 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 reg = <2>; 580 si570_1: clock-generator@5d { /* USER SI570 - u42 */ 581 #clock-cells = <0>; 582 compatible = "silabs,si570"; 583 reg = <0x5d>; 584 temperature-stability = <50>; 585 factory-fout = <300000000>; 586 clock-frequency = <300000000>; 587 clock-output-names = "si570_user"; 588 }; 589 }; 590 i2c@3 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 reg = <3>; 594 si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ 595 #clock-cells = <0>; 596 compatible = "silabs,si570"; 597 reg = <0x5d>; 598 temperature-stability = <50>; /* copy from zc702 */ 599 factory-fout = <156250000>; 600 clock-frequency = <148500000>; 601 clock-output-names = "si570_mgt"; 602 }; 603 }; 604 i2c@4 { 605 #address-cells = <1>; 606 #size-cells = <0>; 607 reg = <4>; 608 si5328: clock-generator@69 {/* SI5328 - u20 */ 609 compatible = "silabs,si5328"; 610 reg = <0x69>; 611 /* 612 * Chip has interrupt present connected to PL 613 * interrupt-parent = <&>; 614 * interrupts = <>; 615 */ 616 }; 617 }; 618 /* 5 - 7 unconnected */ 619 }; 620 621 i2c-mux@75 { 622 compatible = "nxp,pca9548"; /* u135 */ 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <0x75>; 626 627 i2c@0 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 reg = <0>; 631 /* HPC0_IIC */ 632 }; 633 i2c@1 { 634 #address-cells = <1>; 635 #size-cells = <0>; 636 reg = <1>; 637 /* HPC1_IIC */ 638 }; 639 i2c@2 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 reg = <2>; 643 /* SYSMON */ 644 }; 645 i2c@3 { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 reg = <3>; 649 /* DDR4 SODIMM */ 650 }; 651 i2c@4 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 reg = <4>; 655 /* SEP 3 */ 656 }; 657 i2c@5 { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 reg = <5>; 661 /* SEP 2 */ 662 }; 663 i2c@6 { 664 #address-cells = <1>; 665 #size-cells = <0>; 666 reg = <6>; 667 /* SEP 1 */ 668 }; 669 i2c@7 { 670 #address-cells = <1>; 671 #size-cells = <0>; 672 reg = <7>; 673 /* SEP 0 */ 674 }; 675 }; 676}; 677 678&pinctrl0 { 679 status = "okay"; 680 pinctrl_i2c0_default: i2c0-default { 681 mux { 682 groups = "i2c0_3_grp"; 683 function = "i2c0"; 684 }; 685 686 conf { 687 groups = "i2c0_3_grp"; 688 bias-pull-up; 689 slew-rate = <SLEW_RATE_SLOW>; 690 power-source = <IO_STANDARD_LVCMOS18>; 691 }; 692 }; 693 694 pinctrl_i2c0_gpio: i2c0-gpio { 695 mux { 696 groups = "gpio0_14_grp", "gpio0_15_grp"; 697 function = "gpio0"; 698 }; 699 700 conf { 701 groups = "gpio0_14_grp", "gpio0_15_grp"; 702 slew-rate = <SLEW_RATE_SLOW>; 703 power-source = <IO_STANDARD_LVCMOS18>; 704 }; 705 }; 706 707 pinctrl_i2c1_default: i2c1-default { 708 mux { 709 groups = "i2c1_4_grp"; 710 function = "i2c1"; 711 }; 712 713 conf { 714 groups = "i2c1_4_grp"; 715 bias-pull-up; 716 slew-rate = <SLEW_RATE_SLOW>; 717 power-source = <IO_STANDARD_LVCMOS18>; 718 }; 719 }; 720 721 pinctrl_i2c1_gpio: i2c1-gpio { 722 mux { 723 groups = "gpio0_16_grp", "gpio0_17_grp"; 724 function = "gpio0"; 725 }; 726 727 conf { 728 groups = "gpio0_16_grp", "gpio0_17_grp"; 729 slew-rate = <SLEW_RATE_SLOW>; 730 power-source = <IO_STANDARD_LVCMOS18>; 731 }; 732 }; 733 734 pinctrl_uart0_default: uart0-default { 735 mux { 736 groups = "uart0_4_grp"; 737 function = "uart0"; 738 }; 739 740 conf { 741 groups = "uart0_4_grp"; 742 slew-rate = <SLEW_RATE_SLOW>; 743 power-source = <IO_STANDARD_LVCMOS18>; 744 }; 745 746 conf-rx { 747 pins = "MIO18"; 748 bias-high-impedance; 749 }; 750 751 conf-tx { 752 pins = "MIO19"; 753 bias-disable; 754 }; 755 }; 756 757 pinctrl_uart1_default: uart1-default { 758 mux { 759 groups = "uart1_5_grp"; 760 function = "uart1"; 761 }; 762 763 conf { 764 groups = "uart1_5_grp"; 765 slew-rate = <SLEW_RATE_SLOW>; 766 power-source = <IO_STANDARD_LVCMOS18>; 767 }; 768 769 conf-rx { 770 pins = "MIO21"; 771 bias-high-impedance; 772 }; 773 774 conf-tx { 775 pins = "MIO20"; 776 bias-disable; 777 }; 778 }; 779 780 pinctrl_usb0_default: usb0-default { 781 mux { 782 groups = "usb0_0_grp"; 783 function = "usb0"; 784 }; 785 786 conf { 787 groups = "usb0_0_grp"; 788 slew-rate = <SLEW_RATE_SLOW>; 789 power-source = <IO_STANDARD_LVCMOS18>; 790 }; 791 792 conf-rx { 793 pins = "MIO52", "MIO53", "MIO55"; 794 bias-high-impedance; 795 }; 796 797 conf-tx { 798 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 799 "MIO60", "MIO61", "MIO62", "MIO63"; 800 bias-disable; 801 }; 802 }; 803 804 pinctrl_gem3_default: gem3-default { 805 mux { 806 function = "ethernet3"; 807 groups = "ethernet3_0_grp"; 808 }; 809 810 conf { 811 groups = "ethernet3_0_grp"; 812 slew-rate = <SLEW_RATE_SLOW>; 813 power-source = <IO_STANDARD_LVCMOS18>; 814 }; 815 816 conf-rx { 817 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 818 "MIO75"; 819 bias-high-impedance; 820 low-power-disable; 821 }; 822 823 conf-tx { 824 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 825 "MIO69"; 826 bias-disable; 827 low-power-enable; 828 }; 829 830 mux-mdio { 831 function = "mdio3"; 832 groups = "mdio3_0_grp"; 833 }; 834 835 conf-mdio { 836 groups = "mdio3_0_grp"; 837 slew-rate = <SLEW_RATE_SLOW>; 838 power-source = <IO_STANDARD_LVCMOS18>; 839 bias-disable; 840 }; 841 }; 842 843 pinctrl_can1_default: can1-default { 844 mux { 845 function = "can1"; 846 groups = "can1_6_grp"; 847 }; 848 849 conf { 850 groups = "can1_6_grp"; 851 slew-rate = <SLEW_RATE_SLOW>; 852 power-source = <IO_STANDARD_LVCMOS18>; 853 }; 854 855 conf-rx { 856 pins = "MIO25"; 857 bias-high-impedance; 858 }; 859 860 conf-tx { 861 pins = "MIO24"; 862 bias-disable; 863 }; 864 }; 865 866 pinctrl_sdhci1_default: sdhci1-default { 867 mux { 868 groups = "sdio1_0_grp"; 869 function = "sdio1"; 870 }; 871 872 conf { 873 groups = "sdio1_0_grp"; 874 slew-rate = <SLEW_RATE_SLOW>; 875 power-source = <IO_STANDARD_LVCMOS18>; 876 bias-disable; 877 }; 878 879 mux-cd { 880 groups = "sdio1_cd_0_grp"; 881 function = "sdio1_cd"; 882 }; 883 884 conf-cd { 885 groups = "sdio1_cd_0_grp"; 886 bias-high-impedance; 887 bias-pull-up; 888 slew-rate = <SLEW_RATE_SLOW>; 889 power-source = <IO_STANDARD_LVCMOS18>; 890 }; 891 892 mux-wp { 893 groups = "sdio1_wp_0_grp"; 894 function = "sdio1_wp"; 895 }; 896 897 conf-wp { 898 groups = "sdio1_wp_0_grp"; 899 bias-high-impedance; 900 bias-pull-up; 901 slew-rate = <SLEW_RATE_SLOW>; 902 power-source = <IO_STANDARD_LVCMOS18>; 903 }; 904 }; 905 906 pinctrl_gpio_default: gpio-default { 907 mux-sw { 908 function = "gpio0"; 909 groups = "gpio0_22_grp", "gpio0_23_grp"; 910 }; 911 912 conf-sw { 913 groups = "gpio0_22_grp", "gpio0_23_grp"; 914 slew-rate = <SLEW_RATE_SLOW>; 915 power-source = <IO_STANDARD_LVCMOS18>; 916 }; 917 918 mux-msp { 919 function = "gpio0"; 920 groups = "gpio0_13_grp", "gpio0_38_grp"; 921 }; 922 923 conf-msp { 924 groups = "gpio0_13_grp", "gpio0_38_grp"; 925 slew-rate = <SLEW_RATE_SLOW>; 926 power-source = <IO_STANDARD_LVCMOS18>; 927 }; 928 929 conf-pull-up { 930 pins = "MIO22", "MIO23"; 931 bias-pull-up; 932 }; 933 934 conf-pull-none { 935 pins = "MIO13", "MIO38"; 936 bias-disable; 937 }; 938 }; 939}; 940 941&pcie { 942 status = "okay"; 943}; 944 945&psgtr { 946 status = "okay"; 947 /* pcie, sata, usb3, dp */ 948 clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 949 clock-names = "ref0", "ref1", "ref2", "ref3"; 950}; 951 952&qspi { 953 status = "okay"; 954 is-dual = <1>; 955 flash@0 { 956 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 957 #address-cells = <1>; 958 #size-cells = <1>; 959 reg = <0x0>; 960 spi-tx-bus-width = <1>; 961 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 962 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 963 partition@0 { /* for testing purpose */ 964 label = "qspi-fsbl-uboot"; 965 reg = <0x0 0x100000>; 966 }; 967 partition@100000 { /* for testing purpose */ 968 label = "qspi-linux"; 969 reg = <0x100000 0x500000>; 970 }; 971 partition@600000 { /* for testing purpose */ 972 label = "qspi-device-tree"; 973 reg = <0x600000 0x20000>; 974 }; 975 partition@620000 { /* for testing purpose */ 976 label = "qspi-rootfs"; 977 reg = <0x620000 0x5E0000>; 978 }; 979 }; 980}; 981 982&rtc { 983 status = "okay"; 984}; 985 986&sata { 987 status = "okay"; 988 /* SATA OOB timing settings */ 989 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 990 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 991 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 992 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 993 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 994 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 995 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 996 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 997 phy-names = "sata-phy"; 998 phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; 999}; 1000 1001/* SD1 with level shifter */ 1002&sdhci1 { 1003 status = "okay"; 1004 /* 1005 * 1.0 revision has level shifter and this property should be 1006 * removed for supporting UHS mode 1007 */ 1008 no-1-8-v; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&pinctrl_sdhci1_default>; 1011 xlnx,mio-bank = <1>; 1012}; 1013 1014&uart0 { 1015 status = "okay"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&pinctrl_uart0_default>; 1018}; 1019 1020&uart1 { 1021 status = "okay"; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&pinctrl_uart1_default>; 1024}; 1025 1026/* ULPI SMSC USB3320 */ 1027&usb0 { 1028 status = "okay"; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&pinctrl_usb0_default>; 1031}; 1032 1033&dwc3_0 { 1034 status = "okay"; 1035 dr_mode = "host"; 1036 snps,usb3_lpm_capable; 1037 phy-names = "usb3-phy"; 1038 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 1039 maximum-speed = "super-speed"; 1040}; 1041 1042&watchdog0 { 1043 status = "okay"; 1044}; 1045 1046&xilinx_ams { 1047 status = "okay"; 1048}; 1049 1050&ams_ps { 1051 status = "okay"; 1052}; 1053 1054&ams_pl { 1055 status = "okay"; 1056}; 1057 1058&zynqmp_dpdma { 1059 status = "okay"; 1060}; 1061 1062&zynqmp_dpsub { 1063 status = "okay"; 1064 phy-names = "dp-phy0"; 1065 phys = <&psgtr 1 PHY_TYPE_DP 0 3>; 1066}; 1067