1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/power/xlnx-zynqmp-power.h> 17#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 18 19/ { 20 compatible = "xlnx,zynqmp"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 enable-method = "psci"; 32 operating-points-v2 = <&cpu_opp_table>; 33 reg = <0x0>; 34 cpu-idle-states = <&CPU_SLEEP_0>; 35 }; 36 37 cpu1: cpu@1 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 enable-method = "psci"; 41 reg = <0x1>; 42 operating-points-v2 = <&cpu_opp_table>; 43 cpu-idle-states = <&CPU_SLEEP_0>; 44 }; 45 46 cpu2: cpu@2 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 reg = <0x2>; 51 operating-points-v2 = <&cpu_opp_table>; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 operating-points-v2 = <&cpu_opp_table>; 61 cpu-idle-states = <&CPU_SLEEP_0>; 62 }; 63 64 idle-states { 65 entry-method = "psci"; 66 67 CPU_SLEEP_0: cpu-sleep-0 { 68 compatible = "arm,idle-state"; 69 arm,psci-suspend-param = <0x40000000>; 70 local-timer-stop; 71 entry-latency-us = <300>; 72 exit-latency-us = <600>; 73 min-residency-us = <10000>; 74 }; 75 }; 76 }; 77 78 cpu_opp_table: cpu-opp-table { 79 compatible = "operating-points-v2"; 80 opp-shared; 81 opp00 { 82 opp-hz = /bits/ 64 <1199999988>; 83 opp-microvolt = <1000000>; 84 clock-latency-ns = <500000>; 85 }; 86 opp01 { 87 opp-hz = /bits/ 64 <599999994>; 88 opp-microvolt = <1000000>; 89 clock-latency-ns = <500000>; 90 }; 91 opp02 { 92 opp-hz = /bits/ 64 <399999996>; 93 opp-microvolt = <1000000>; 94 clock-latency-ns = <500000>; 95 }; 96 opp03 { 97 opp-hz = /bits/ 64 <299999997>; 98 opp-microvolt = <1000000>; 99 clock-latency-ns = <500000>; 100 }; 101 }; 102 103 zynqmp_ipi { 104 u-boot,dm-pre-reloc; 105 compatible = "xlnx,zynqmp-ipi-mailbox"; 106 interrupt-parent = <&gic>; 107 interrupts = <0 35 4>; 108 xlnx,ipi-id = <0>; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 113 ipi_mailbox_pmu1: mailbox@ff990400 { 114 u-boot,dm-pre-reloc; 115 reg = <0x0 0xff9905c0 0x0 0x20>, 116 <0x0 0xff9905e0 0x0 0x20>, 117 <0x0 0xff990e80 0x0 0x20>, 118 <0x0 0xff990ea0 0x0 0x20>; 119 reg-names = "local_request_region", 120 "local_response_region", 121 "remote_request_region", 122 "remote_response_region"; 123 #mbox-cells = <1>; 124 xlnx,ipi-id = <4>; 125 }; 126 }; 127 128 dcc: dcc { 129 compatible = "arm,dcc"; 130 status = "disabled"; 131 u-boot,dm-pre-reloc; 132 }; 133 134 pmu { 135 compatible = "arm,armv8-pmuv3"; 136 interrupt-parent = <&gic>; 137 interrupts = <0 143 4>, 138 <0 144 4>, 139 <0 145 4>, 140 <0 146 4>; 141 }; 142 143 psci { 144 compatible = "arm,psci-0.2"; 145 method = "smc"; 146 }; 147 148 firmware { 149 zynqmp_firmware: zynqmp-firmware { 150 compatible = "xlnx,zynqmp-firmware"; 151 #power-domain-cells = <1>; 152 method = "smc"; 153 u-boot,dm-pre-reloc; 154 155 zynqmp_power: zynqmp-power { 156 u-boot,dm-pre-reloc; 157 compatible = "xlnx,zynqmp-power"; 158 interrupt-parent = <&gic>; 159 interrupts = <0 35 4>; 160 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 161 mbox-names = "tx", "rx"; 162 }; 163 164 nvmem_firmware { 165 compatible = "xlnx,zynqmp-nvmem-fw"; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 soc_revision: soc_revision@0 { 170 reg = <0x0 0x4>; 171 }; 172 }; 173 174 zynqmp_pcap: pcap { 175 compatible = "xlnx,zynqmp-pcap-fpga"; 176 clock-names = "ref_clk"; 177 }; 178 179 xlnx_aes: zynqmp-aes { 180 compatible = "xlnx,zynqmp-aes"; 181 }; 182 183 zynqmp_reset: reset-controller { 184 compatible = "xlnx,zynqmp-reset"; 185 #reset-cells = <1>; 186 }; 187 188 pinctrl0: pinctrl { 189 compatible = "xlnx,zynqmp-pinctrl"; 190 status = "disabled"; 191 }; 192 }; 193 }; 194 195 timer { 196 compatible = "arm,armv8-timer"; 197 interrupt-parent = <&gic>; 198 interrupts = <1 13 0xf08>, 199 <1 14 0xf08>, 200 <1 11 0xf08>, 201 <1 10 0xf08>; 202 }; 203 204 edac { 205 compatible = "arm,cortex-a53-edac"; 206 }; 207 208 fpga_full: fpga-full { 209 compatible = "fpga-region"; 210 fpga-mgr = <&zynqmp_pcap>; 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 }; 215 216 amba: axi { 217 compatible = "simple-bus"; 218 u-boot,dm-pre-reloc; 219 #address-cells = <2>; 220 #size-cells = <2>; 221 ranges; 222 223 can0: can@ff060000 { 224 compatible = "xlnx,zynq-can-1.0"; 225 status = "disabled"; 226 clock-names = "can_clk", "pclk"; 227 reg = <0x0 0xff060000 0x0 0x1000>; 228 interrupts = <0 23 4>; 229 interrupt-parent = <&gic>; 230 tx-fifo-depth = <0x40>; 231 rx-fifo-depth = <0x40>; 232 power-domains = <&zynqmp_firmware PD_CAN_0>; 233 }; 234 235 can1: can@ff070000 { 236 compatible = "xlnx,zynq-can-1.0"; 237 status = "disabled"; 238 clock-names = "can_clk", "pclk"; 239 reg = <0x0 0xff070000 0x0 0x1000>; 240 interrupts = <0 24 4>; 241 interrupt-parent = <&gic>; 242 tx-fifo-depth = <0x40>; 243 rx-fifo-depth = <0x40>; 244 power-domains = <&zynqmp_firmware PD_CAN_1>; 245 }; 246 247 cci: cci@fd6e0000 { 248 compatible = "arm,cci-400"; 249 reg = <0x0 0xfd6e0000 0x0 0x9000>; 250 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 254 pmu@9000 { 255 compatible = "arm,cci-400-pmu,r1"; 256 reg = <0x9000 0x5000>; 257 interrupt-parent = <&gic>; 258 interrupts = <0 123 4>, 259 <0 123 4>, 260 <0 123 4>, 261 <0 123 4>, 262 <0 123 4>; 263 }; 264 }; 265 266 /* GDMA */ 267 fpd_dma_chan1: dma@fd500000 { 268 status = "disabled"; 269 compatible = "xlnx,zynqmp-dma-1.0"; 270 reg = <0x0 0xfd500000 0x0 0x1000>; 271 interrupt-parent = <&gic>; 272 interrupts = <0 124 4>; 273 clock-names = "clk_main", "clk_apb"; 274 xlnx,bus-width = <128>; 275 #stream-id-cells = <1>; 276 iommus = <&smmu 0x14e8>; 277 power-domains = <&zynqmp_firmware PD_GDMA>; 278 }; 279 280 fpd_dma_chan2: dma@fd510000 { 281 status = "disabled"; 282 compatible = "xlnx,zynqmp-dma-1.0"; 283 reg = <0x0 0xfd510000 0x0 0x1000>; 284 interrupt-parent = <&gic>; 285 interrupts = <0 125 4>; 286 clock-names = "clk_main", "clk_apb"; 287 xlnx,bus-width = <128>; 288 #stream-id-cells = <1>; 289 iommus = <&smmu 0x14e9>; 290 power-domains = <&zynqmp_firmware PD_GDMA>; 291 }; 292 293 fpd_dma_chan3: dma@fd520000 { 294 status = "disabled"; 295 compatible = "xlnx,zynqmp-dma-1.0"; 296 reg = <0x0 0xfd520000 0x0 0x1000>; 297 interrupt-parent = <&gic>; 298 interrupts = <0 126 4>; 299 clock-names = "clk_main", "clk_apb"; 300 xlnx,bus-width = <128>; 301 #stream-id-cells = <1>; 302 iommus = <&smmu 0x14ea>; 303 power-domains = <&zynqmp_firmware PD_GDMA>; 304 }; 305 306 fpd_dma_chan4: dma@fd530000 { 307 status = "disabled"; 308 compatible = "xlnx,zynqmp-dma-1.0"; 309 reg = <0x0 0xfd530000 0x0 0x1000>; 310 interrupt-parent = <&gic>; 311 interrupts = <0 127 4>; 312 clock-names = "clk_main", "clk_apb"; 313 xlnx,bus-width = <128>; 314 #stream-id-cells = <1>; 315 iommus = <&smmu 0x14eb>; 316 power-domains = <&zynqmp_firmware PD_GDMA>; 317 }; 318 319 fpd_dma_chan5: dma@fd540000 { 320 status = "disabled"; 321 compatible = "xlnx,zynqmp-dma-1.0"; 322 reg = <0x0 0xfd540000 0x0 0x1000>; 323 interrupt-parent = <&gic>; 324 interrupts = <0 128 4>; 325 clock-names = "clk_main", "clk_apb"; 326 xlnx,bus-width = <128>; 327 #stream-id-cells = <1>; 328 iommus = <&smmu 0x14ec>; 329 power-domains = <&zynqmp_firmware PD_GDMA>; 330 }; 331 332 fpd_dma_chan6: dma@fd550000 { 333 status = "disabled"; 334 compatible = "xlnx,zynqmp-dma-1.0"; 335 reg = <0x0 0xfd550000 0x0 0x1000>; 336 interrupt-parent = <&gic>; 337 interrupts = <0 129 4>; 338 clock-names = "clk_main", "clk_apb"; 339 xlnx,bus-width = <128>; 340 #stream-id-cells = <1>; 341 iommus = <&smmu 0x14ed>; 342 power-domains = <&zynqmp_firmware PD_GDMA>; 343 }; 344 345 fpd_dma_chan7: dma@fd560000 { 346 status = "disabled"; 347 compatible = "xlnx,zynqmp-dma-1.0"; 348 reg = <0x0 0xfd560000 0x0 0x1000>; 349 interrupt-parent = <&gic>; 350 interrupts = <0 130 4>; 351 clock-names = "clk_main", "clk_apb"; 352 xlnx,bus-width = <128>; 353 #stream-id-cells = <1>; 354 iommus = <&smmu 0x14ee>; 355 power-domains = <&zynqmp_firmware PD_GDMA>; 356 }; 357 358 fpd_dma_chan8: dma@fd570000 { 359 status = "disabled"; 360 compatible = "xlnx,zynqmp-dma-1.0"; 361 reg = <0x0 0xfd570000 0x0 0x1000>; 362 interrupt-parent = <&gic>; 363 interrupts = <0 131 4>; 364 clock-names = "clk_main", "clk_apb"; 365 xlnx,bus-width = <128>; 366 #stream-id-cells = <1>; 367 iommus = <&smmu 0x14ef>; 368 power-domains = <&zynqmp_firmware PD_GDMA>; 369 }; 370 371 gic: interrupt-controller@f9010000 { 372 compatible = "arm,gic-400"; 373 #interrupt-cells = <3>; 374 reg = <0x0 0xf9010000 0x0 0x10000>, 375 <0x0 0xf9020000 0x0 0x20000>, 376 <0x0 0xf9040000 0x0 0x20000>, 377 <0x0 0xf9060000 0x0 0x20000>; 378 interrupt-controller; 379 interrupt-parent = <&gic>; 380 interrupts = <1 9 0xf04>; 381 }; 382 383 gpu: gpu@fd4b0000 { 384 status = "disabled"; 385 compatible = "arm,mali-400", "arm,mali-utgard"; 386 reg = <0x0 0xfd4b0000 0x0 0x10000>; 387 interrupt-parent = <&gic>; 388 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 389 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 390 clock-names = "gpu", "gpu_pp0", "gpu_pp1"; 391 power-domains = <&zynqmp_firmware PD_GPU>; 392 }; 393 394 /* LPDDMA default allows only secured access. inorder to enable 395 * These dma channels, Users should ensure that these dma 396 * Channels are allowed for non secure access. 397 */ 398 lpd_dma_chan1: dma@ffa80000 { 399 status = "disabled"; 400 compatible = "xlnx,zynqmp-dma-1.0"; 401 reg = <0x0 0xffa80000 0x0 0x1000>; 402 interrupt-parent = <&gic>; 403 interrupts = <0 77 4>; 404 clock-names = "clk_main", "clk_apb"; 405 xlnx,bus-width = <64>; 406 #stream-id-cells = <1>; 407 iommus = <&smmu 0x868>; 408 power-domains = <&zynqmp_firmware PD_ADMA>; 409 }; 410 411 lpd_dma_chan2: dma@ffa90000 { 412 status = "disabled"; 413 compatible = "xlnx,zynqmp-dma-1.0"; 414 reg = <0x0 0xffa90000 0x0 0x1000>; 415 interrupt-parent = <&gic>; 416 interrupts = <0 78 4>; 417 clock-names = "clk_main", "clk_apb"; 418 xlnx,bus-width = <64>; 419 #stream-id-cells = <1>; 420 iommus = <&smmu 0x869>; 421 power-domains = <&zynqmp_firmware PD_ADMA>; 422 }; 423 424 lpd_dma_chan3: dma@ffaa0000 { 425 status = "disabled"; 426 compatible = "xlnx,zynqmp-dma-1.0"; 427 reg = <0x0 0xffaa0000 0x0 0x1000>; 428 interrupt-parent = <&gic>; 429 interrupts = <0 79 4>; 430 clock-names = "clk_main", "clk_apb"; 431 xlnx,bus-width = <64>; 432 #stream-id-cells = <1>; 433 iommus = <&smmu 0x86a>; 434 power-domains = <&zynqmp_firmware PD_ADMA>; 435 }; 436 437 lpd_dma_chan4: dma@ffab0000 { 438 status = "disabled"; 439 compatible = "xlnx,zynqmp-dma-1.0"; 440 reg = <0x0 0xffab0000 0x0 0x1000>; 441 interrupt-parent = <&gic>; 442 interrupts = <0 80 4>; 443 clock-names = "clk_main", "clk_apb"; 444 xlnx,bus-width = <64>; 445 #stream-id-cells = <1>; 446 iommus = <&smmu 0x86b>; 447 power-domains = <&zynqmp_firmware PD_ADMA>; 448 }; 449 450 lpd_dma_chan5: dma@ffac0000 { 451 status = "disabled"; 452 compatible = "xlnx,zynqmp-dma-1.0"; 453 reg = <0x0 0xffac0000 0x0 0x1000>; 454 interrupt-parent = <&gic>; 455 interrupts = <0 81 4>; 456 clock-names = "clk_main", "clk_apb"; 457 xlnx,bus-width = <64>; 458 #stream-id-cells = <1>; 459 iommus = <&smmu 0x86c>; 460 power-domains = <&zynqmp_firmware PD_ADMA>; 461 }; 462 463 lpd_dma_chan6: dma@ffad0000 { 464 status = "disabled"; 465 compatible = "xlnx,zynqmp-dma-1.0"; 466 reg = <0x0 0xffad0000 0x0 0x1000>; 467 interrupt-parent = <&gic>; 468 interrupts = <0 82 4>; 469 clock-names = "clk_main", "clk_apb"; 470 xlnx,bus-width = <64>; 471 #stream-id-cells = <1>; 472 iommus = <&smmu 0x86d>; 473 power-domains = <&zynqmp_firmware PD_ADMA>; 474 }; 475 476 lpd_dma_chan7: dma@ffae0000 { 477 status = "disabled"; 478 compatible = "xlnx,zynqmp-dma-1.0"; 479 reg = <0x0 0xffae0000 0x0 0x1000>; 480 interrupt-parent = <&gic>; 481 interrupts = <0 83 4>; 482 clock-names = "clk_main", "clk_apb"; 483 xlnx,bus-width = <64>; 484 #stream-id-cells = <1>; 485 iommus = <&smmu 0x86e>; 486 power-domains = <&zynqmp_firmware PD_ADMA>; 487 }; 488 489 lpd_dma_chan8: dma@ffaf0000 { 490 status = "disabled"; 491 compatible = "xlnx,zynqmp-dma-1.0"; 492 reg = <0x0 0xffaf0000 0x0 0x1000>; 493 interrupt-parent = <&gic>; 494 interrupts = <0 84 4>; 495 clock-names = "clk_main", "clk_apb"; 496 xlnx,bus-width = <64>; 497 #stream-id-cells = <1>; 498 iommus = <&smmu 0x86f>; 499 power-domains = <&zynqmp_firmware PD_ADMA>; 500 }; 501 502 mc: memory-controller@fd070000 { 503 compatible = "xlnx,zynqmp-ddrc-2.40a"; 504 reg = <0x0 0xfd070000 0x0 0x30000>; 505 interrupt-parent = <&gic>; 506 interrupts = <0 112 4>; 507 }; 508 509 nand0: nand-controller@ff100000 { 510 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 511 status = "disabled"; 512 reg = <0x0 0xff100000 0x0 0x1000>; 513 clock-names = "controller", "bus"; 514 interrupt-parent = <&gic>; 515 interrupts = <0 14 4>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 #stream-id-cells = <1>; 519 iommus = <&smmu 0x872>; 520 power-domains = <&zynqmp_firmware PD_NAND>; 521 }; 522 523 gem0: ethernet@ff0b0000 { 524 compatible = "cdns,zynqmp-gem", "cdns,gem"; 525 status = "disabled"; 526 interrupt-parent = <&gic>; 527 interrupts = <0 57 4>, <0 57 4>; 528 reg = <0x0 0xff0b0000 0x0 0x1000>; 529 clock-names = "pclk", "hclk", "tx_clk"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #stream-id-cells = <1>; 533 iommus = <&smmu 0x874>; 534 power-domains = <&zynqmp_firmware PD_ETH_0>; 535 }; 536 537 gem1: ethernet@ff0c0000 { 538 compatible = "cdns,zynqmp-gem", "cdns,gem"; 539 status = "disabled"; 540 interrupt-parent = <&gic>; 541 interrupts = <0 59 4>, <0 59 4>; 542 reg = <0x0 0xff0c0000 0x0 0x1000>; 543 clock-names = "pclk", "hclk", "tx_clk"; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 #stream-id-cells = <1>; 547 iommus = <&smmu 0x875>; 548 power-domains = <&zynqmp_firmware PD_ETH_1>; 549 }; 550 551 gem2: ethernet@ff0d0000 { 552 compatible = "cdns,zynqmp-gem", "cdns,gem"; 553 status = "disabled"; 554 interrupt-parent = <&gic>; 555 interrupts = <0 61 4>, <0 61 4>; 556 reg = <0x0 0xff0d0000 0x0 0x1000>; 557 clock-names = "pclk", "hclk", "tx_clk"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 #stream-id-cells = <1>; 561 iommus = <&smmu 0x876>; 562 power-domains = <&zynqmp_firmware PD_ETH_2>; 563 }; 564 565 gem3: ethernet@ff0e0000 { 566 compatible = "cdns,zynqmp-gem", "cdns,gem"; 567 status = "disabled"; 568 interrupt-parent = <&gic>; 569 interrupts = <0 63 4>, <0 63 4>; 570 reg = <0x0 0xff0e0000 0x0 0x1000>; 571 clock-names = "pclk", "hclk", "tx_clk"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 #stream-id-cells = <1>; 575 iommus = <&smmu 0x877>; 576 power-domains = <&zynqmp_firmware PD_ETH_3>; 577 }; 578 579 gpio: gpio@ff0a0000 { 580 compatible = "xlnx,zynqmp-gpio-1.0"; 581 status = "disabled"; 582 #gpio-cells = <0x2>; 583 gpio-controller; 584 interrupt-parent = <&gic>; 585 interrupts = <0 16 4>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 reg = <0x0 0xff0a0000 0x0 0x1000>; 589 power-domains = <&zynqmp_firmware PD_GPIO>; 590 }; 591 592 i2c0: i2c@ff020000 { 593 compatible = "cdns,i2c-r1p14"; 594 status = "disabled"; 595 interrupt-parent = <&gic>; 596 interrupts = <0 17 4>; 597 reg = <0x0 0xff020000 0x0 0x1000>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 power-domains = <&zynqmp_firmware PD_I2C_0>; 601 }; 602 603 i2c1: i2c@ff030000 { 604 compatible = "cdns,i2c-r1p14"; 605 status = "disabled"; 606 interrupt-parent = <&gic>; 607 interrupts = <0 18 4>; 608 reg = <0x0 0xff030000 0x0 0x1000>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 power-domains = <&zynqmp_firmware PD_I2C_1>; 612 }; 613 614 ocm: memory-controller@ff960000 { 615 compatible = "xlnx,zynqmp-ocmc-1.0"; 616 reg = <0x0 0xff960000 0x0 0x1000>; 617 interrupt-parent = <&gic>; 618 interrupts = <0 10 4>; 619 }; 620 621 pcie: pcie@fd0e0000 { 622 compatible = "xlnx,nwl-pcie-2.11"; 623 status = "disabled"; 624 #address-cells = <3>; 625 #size-cells = <2>; 626 #interrupt-cells = <1>; 627 msi-controller; 628 device_type = "pci"; 629 interrupt-parent = <&gic>; 630 interrupts = <0 118 4>, 631 <0 117 4>, 632 <0 116 4>, 633 <0 115 4>, /* MSI_1 [63...32] */ 634 <0 114 4>; /* MSI_0 [31...0] */ 635 interrupt-names = "misc", "dummy", "intx", 636 "msi1", "msi0"; 637 msi-parent = <&pcie>; 638 reg = <0x0 0xfd0e0000 0x0 0x1000>, 639 <0x0 0xfd480000 0x0 0x1000>, 640 <0x80 0x00000000 0x0 0x1000000>; 641 reg-names = "breg", "pcireg", "cfg"; 642 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 643 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 644 bus-range = <0x00 0xff>; 645 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 646 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 647 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 648 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 649 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 650 power-domains = <&zynqmp_firmware PD_PCIE>; 651 pcie_intc: legacy-interrupt-controller { 652 interrupt-controller; 653 #address-cells = <0>; 654 #interrupt-cells = <1>; 655 }; 656 }; 657 658 qspi: spi@ff0f0000 { 659 u-boot,dm-pre-reloc; 660 compatible = "xlnx,zynqmp-qspi-1.0"; 661 status = "disabled"; 662 clock-names = "ref_clk", "pclk"; 663 interrupts = <0 15 4>; 664 interrupt-parent = <&gic>; 665 num-cs = <1>; 666 reg = <0x0 0xff0f0000 0x0 0x1000>, 667 <0x0 0xc0000000 0x0 0x8000000>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 #stream-id-cells = <1>; 671 iommus = <&smmu 0x873>; 672 power-domains = <&zynqmp_firmware PD_QSPI>; 673 }; 674 675 psgtr: phy@fd400000 { 676 compatible = "xlnx,zynqmp-psgtr-v1.1"; 677 status = "disabled"; 678 reg = <0x0 0xfd400000 0x0 0x40000>, 679 <0x0 0xfd3d0000 0x0 0x1000>; 680 reg-names = "serdes", "siou"; 681 #phy-cells = <4>; 682 }; 683 684 rtc: rtc@ffa60000 { 685 compatible = "xlnx,zynqmp-rtc"; 686 status = "disabled"; 687 reg = <0x0 0xffa60000 0x0 0x100>; 688 interrupt-parent = <&gic>; 689 interrupts = <0 26 4>, <0 27 4>; 690 interrupt-names = "alarm", "sec"; 691 calibration = <0x8000>; 692 }; 693 694 sata: ahci@fd0c0000 { 695 compatible = "ceva,ahci-1v84"; 696 status = "disabled"; 697 reg = <0x0 0xfd0c0000 0x0 0x2000>; 698 interrupt-parent = <&gic>; 699 interrupts = <0 133 4>; 700 power-domains = <&zynqmp_firmware PD_SATA>; 701 #stream-id-cells = <4>; 702 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 703 <&smmu 0x4c2>, <&smmu 0x4c3>; 704 /* dma-coherent; */ 705 }; 706 707 sdhci0: mmc@ff160000 { 708 u-boot,dm-pre-reloc; 709 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 710 status = "disabled"; 711 interrupt-parent = <&gic>; 712 interrupts = <0 48 4>; 713 reg = <0x0 0xff160000 0x0 0x1000>; 714 clock-names = "clk_xin", "clk_ahb"; 715 xlnx,device_id = <0>; 716 #stream-id-cells = <1>; 717 iommus = <&smmu 0x870>; 718 nvmem-cells = <&soc_revision>; 719 nvmem-cell-names = "soc_revision"; 720 #clock-cells = <1>; 721 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 722 power-domains = <&zynqmp_firmware PD_SD_0>; 723 }; 724 725 sdhci1: mmc@ff170000 { 726 u-boot,dm-pre-reloc; 727 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 728 status = "disabled"; 729 interrupt-parent = <&gic>; 730 interrupts = <0 49 4>; 731 reg = <0x0 0xff170000 0x0 0x1000>; 732 clock-names = "clk_xin", "clk_ahb"; 733 xlnx,device_id = <1>; 734 #stream-id-cells = <1>; 735 iommus = <&smmu 0x871>; 736 nvmem-cells = <&soc_revision>; 737 nvmem-cell-names = "soc_revision"; 738 #clock-cells = <1>; 739 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 740 power-domains = <&zynqmp_firmware PD_SD_1>; 741 }; 742 743 smmu: iommu@fd800000 { 744 compatible = "arm,mmu-500"; 745 reg = <0x0 0xfd800000 0x0 0x20000>; 746 #iommu-cells = <1>; 747 status = "disabled"; 748 #global-interrupts = <1>; 749 interrupt-parent = <&gic>; 750 interrupts = <0 155 4>, 751 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 752 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 753 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 754 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 755 }; 756 757 spi0: spi@ff040000 { 758 compatible = "cdns,spi-r1p6"; 759 status = "disabled"; 760 interrupt-parent = <&gic>; 761 interrupts = <0 19 4>; 762 reg = <0x0 0xff040000 0x0 0x1000>; 763 clock-names = "ref_clk", "pclk"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 power-domains = <&zynqmp_firmware PD_SPI_0>; 767 }; 768 769 spi1: spi@ff050000 { 770 compatible = "cdns,spi-r1p6"; 771 status = "disabled"; 772 interrupt-parent = <&gic>; 773 interrupts = <0 20 4>; 774 reg = <0x0 0xff050000 0x0 0x1000>; 775 clock-names = "ref_clk", "pclk"; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 power-domains = <&zynqmp_firmware PD_SPI_1>; 779 }; 780 781 ttc0: timer@ff110000 { 782 compatible = "cdns,ttc"; 783 status = "disabled"; 784 interrupt-parent = <&gic>; 785 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 786 reg = <0x0 0xff110000 0x0 0x1000>; 787 timer-width = <32>; 788 power-domains = <&zynqmp_firmware PD_TTC_0>; 789 }; 790 791 ttc1: timer@ff120000 { 792 compatible = "cdns,ttc"; 793 status = "disabled"; 794 interrupt-parent = <&gic>; 795 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 796 reg = <0x0 0xff120000 0x0 0x1000>; 797 timer-width = <32>; 798 power-domains = <&zynqmp_firmware PD_TTC_1>; 799 }; 800 801 ttc2: timer@ff130000 { 802 compatible = "cdns,ttc"; 803 status = "disabled"; 804 interrupt-parent = <&gic>; 805 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 806 reg = <0x0 0xff130000 0x0 0x1000>; 807 timer-width = <32>; 808 power-domains = <&zynqmp_firmware PD_TTC_2>; 809 }; 810 811 ttc3: timer@ff140000 { 812 compatible = "cdns,ttc"; 813 status = "disabled"; 814 interrupt-parent = <&gic>; 815 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 816 reg = <0x0 0xff140000 0x0 0x1000>; 817 timer-width = <32>; 818 power-domains = <&zynqmp_firmware PD_TTC_3>; 819 }; 820 821 uart0: serial@ff000000 { 822 u-boot,dm-pre-reloc; 823 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 824 status = "disabled"; 825 interrupt-parent = <&gic>; 826 interrupts = <0 21 4>; 827 reg = <0x0 0xff000000 0x0 0x1000>; 828 clock-names = "uart_clk", "pclk"; 829 power-domains = <&zynqmp_firmware PD_UART_0>; 830 }; 831 832 uart1: serial@ff010000 { 833 u-boot,dm-pre-reloc; 834 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 835 status = "disabled"; 836 interrupt-parent = <&gic>; 837 interrupts = <0 22 4>; 838 reg = <0x0 0xff010000 0x0 0x1000>; 839 clock-names = "uart_clk", "pclk"; 840 power-domains = <&zynqmp_firmware PD_UART_1>; 841 }; 842 843 usb0: usb0@ff9d0000 { 844 #address-cells = <2>; 845 #size-cells = <2>; 846 status = "disabled"; 847 compatible = "xlnx,zynqmp-dwc3"; 848 reg = <0x0 0xff9d0000 0x0 0x100>; 849 clock-names = "bus_clk", "ref_clk"; 850 power-domains = <&zynqmp_firmware PD_USB_0>; 851 ranges; 852 nvmem-cells = <&soc_revision>; 853 nvmem-cell-names = "soc_revision"; 854 855 dwc3_0: dwc3@fe200000 { 856 compatible = "snps,dwc3"; 857 status = "disabled"; 858 reg = <0x0 0xfe200000 0x0 0x40000>; 859 interrupt-parent = <&gic>; 860 interrupts = <0 65 4>, <0 69 4>; 861 #stream-id-cells = <1>; 862 iommus = <&smmu 0x860>; 863 snps,quirk-frame-length-adjustment = <0x20>; 864 snps,refclk_fladj; 865 /* dma-coherent; */ 866 }; 867 }; 868 869 usb1: usb1@ff9e0000 { 870 #address-cells = <2>; 871 #size-cells = <2>; 872 status = "disabled"; 873 compatible = "xlnx,zynqmp-dwc3"; 874 reg = <0x0 0xff9e0000 0x0 0x100>; 875 clock-names = "bus_clk", "ref_clk"; 876 power-domains = <&zynqmp_firmware PD_USB_1>; 877 ranges; 878 nvmem-cells = <&soc_revision>; 879 nvmem-cell-names = "soc_revision"; 880 881 dwc3_1: dwc3@fe300000 { 882 compatible = "snps,dwc3"; 883 status = "disabled"; 884 reg = <0x0 0xfe300000 0x0 0x40000>; 885 interrupt-parent = <&gic>; 886 interrupts = <0 70 4>, <0 74 4>; 887 #stream-id-cells = <1>; 888 iommus = <&smmu 0x861>; 889 snps,quirk-frame-length-adjustment = <0x20>; 890 snps,refclk_fladj; 891 /* dma-coherent; */ 892 }; 893 }; 894 895 watchdog0: watchdog@fd4d0000 { 896 compatible = "cdns,wdt-r1p2"; 897 status = "disabled"; 898 interrupt-parent = <&gic>; 899 interrupts = <0 113 1>; 900 reg = <0x0 0xfd4d0000 0x0 0x1000>; 901 timeout-sec = <60>; 902 reset-on-timeout; 903 }; 904 905 lpd_watchdog: watchdog@ff150000 { 906 compatible = "cdns,wdt-r1p2"; 907 status = "disabled"; 908 interrupt-parent = <&gic>; 909 interrupts = <0 52 1>; 910 reg = <0x0 0xff150000 0x0 0x1000>; 911 timeout-sec = <10>; 912 }; 913 914 xilinx_ams: ams@ffa50000 { 915 compatible = "xlnx,zynqmp-ams"; 916 status = "disabled"; 917 interrupt-parent = <&gic>; 918 interrupts = <0 56 4>; 919 interrupt-names = "ams-irq"; 920 reg = <0x0 0xffa50000 0x0 0x800>; 921 reg-names = "ams-base"; 922 #address-cells = <2>; 923 #size-cells = <2>; 924 #io-channel-cells = <1>; 925 ranges; 926 927 ams_ps: ams_ps@ffa50800 { 928 compatible = "xlnx,zynqmp-ams-ps"; 929 status = "disabled"; 930 reg = <0x0 0xffa50800 0x0 0x400>; 931 }; 932 933 ams_pl: ams_pl@ffa50c00 { 934 compatible = "xlnx,zynqmp-ams-pl"; 935 status = "disabled"; 936 reg = <0x0 0xffa50c00 0x0 0x400>; 937 }; 938 }; 939 940 zynqmp_dpdma: dma-controller@fd4c0000 { 941 compatible = "xlnx,zynqmp-dpdma"; 942 status = "disabled"; 943 reg = <0x0 0xfd4c0000 0x0 0x1000>; 944 interrupts = <0 122 4>; 945 interrupt-parent = <&gic>; 946 clock-names = "axi_clk"; 947 power-domains = <&zynqmp_firmware PD_DP>; 948 #dma-cells = <1>; 949 }; 950 951 zynqmp_dpsub: display@fd4a0000 { 952 compatible = "xlnx,zynqmp-dpsub-1.7"; 953 status = "disabled"; 954 reg = <0x0 0xfd4a0000 0x0 0x1000>, 955 <0x0 0xfd4aa000 0x0 0x1000>, 956 <0x0 0xfd4ab000 0x0 0x1000>, 957 <0x0 0xfd4ac000 0x0 0x1000>; 958 reg-names = "dp", "blend", "av_buf", "aud"; 959 interrupts = <0 119 4>; 960 interrupt-parent = <&gic>; 961 clock-names = "dp_apb_clk", "dp_aud_clk", 962 "dp_vtc_pixel_clk_in"; 963 power-domains = <&zynqmp_firmware PD_DP>; 964 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 965 dma-names = "vid0", "vid1", "vid2", "gfx0"; 966 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 967 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 968 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 969 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 970 }; 971 }; 972}; 973