1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 */
5 #define LOG_CATEGORY UCLASS_CLK
6
7 #include <common.h>
8 #include <dm.h>
9 /* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
10 #include <div64.h>
11 #include <log.h>
12 #include <serial.h>
13 #include <asm/io.h>
14 #include <dt-bindings/clock/k210-sysctl.h>
15 #include <kendryte/pll.h>
16 #include <linux/bitfield.h>
17 #include <linux/clk-provider.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20
21 #define CLK_K210_PLL "k210_clk_pll"
22
23 #ifdef CONFIG_CLK_K210_SET_RATE
24 static int k210_pll_enable(struct clk *clk);
25 static int k210_pll_disable(struct clk *clk);
26
27 /*
28 * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
29 * General-Purpose PLL. The logical layout of the PLL with internal feedback is
30 * approximately the following:
31 *
32 * +---------------+
33 * |reference clock|
34 * +---------------+
35 * |
36 * v
37 * +--+
38 * |/r|
39 * +--+
40 * |
41 * v
42 * +-------------+
43 * |divided clock|
44 * +-------------+
45 * |
46 * v
47 * +--------------+
48 * |phase detector|<---+
49 * +--------------+ |
50 * | |
51 * v +--------------+
52 * +---+ |feedback clock|
53 * |VCO| +--------------+
54 * +---+ ^
55 * | +--+ |
56 * +--->|/f|---+
57 * | +--+
58 * v
59 * +---+
60 * |/od|
61 * +---+
62 * |
63 * v
64 * +------+
65 * |output|
66 * +------+
67 *
68 * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
69 * the effect of the division by f is to multiply the input frequency. The
70 * equation for the output rate is
71 * rate = (rate_in * f) / (r * od).
72 * Moving knowns to one side of the equation, we get
73 * rate / rate_in = f / (r * od)
74 * Rearranging slightly,
75 * abs_error = abs((rate / rate_in) - (f / (r * od))).
76 * To get relative, error, we divide by the expected ratio
77 * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
78 * Simplifying,
79 * error = abs(1 - f / (r * od)) / (rate / rate_in)
80 * error = abs(1 - (f * rate_in) / (r * od * rate))
81 * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
82 * error = abs((f * inv_ratio) / (r * od) - 1)
83 * This is the error used in evaluating parameters.
84 *
85 * r and od are four bits each, while f is six bits. Because r and od are
86 * multiplied together, instead of the full 256 values possible if both bits
87 * were used fully, there are only 97 distinct products. Combined with f, there
88 * are 6208 theoretical settings for the PLL. However, most of these settings
89 * can be ruled out immediately because they do not have the correct ratio.
90 *
91 * In addition to the constraint of approximating the desired ratio, parameters
92 * must also keep internal pll frequencies within acceptable ranges. The divided
93 * clock's minimum and maximum frequencies have a ratio of around 128. This
94 * leaves fairly substantial room to work with, especially since the only
95 * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
96 * of 5, which is considerably more restrictive.
97 *
98 * The r and od factors are stored in a table. This is to make it easy to find
99 * the next-largest product. Some products have multiple factorizations, but
100 * only when one factor has at least a 2.5x ratio to the factors of the other
101 * factorization. This is because any smaller ratio would not make a difference
102 * when ensuring the VCO's frequency is within spec.
103 *
104 * Throughout the calculation function, fixed point arithmetic is used. Because
105 * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
106 * 32.32 fixed-point numbers are used to represent ratios. In general, to
107 * implement division, the numerator is first multiplied by 2^32. This gives a
108 * result where the whole number part is in the upper 32 bits, and the fraction
109 * is in the lower 32 bits.
110 *
111 * In general, rounding is done to the closest integer. This helps find the best
112 * approximation for the ratio. Rounding in one direction (e.g down) could cause
113 * the function to miss a better ratio with one of the parameters increased by
114 * one.
115 */
116
117 /*
118 * The factors table was generated with the following python code:
119 *
120 * def p(x, y):
121 * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
122 *
123 * factors = {}
124 * for i in range(1, 17):
125 * for j in range(1, 17):
126 * fs = factors.get(i*j) or []
127 * if fs == [] or all([
128 * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
129 * for (x, y) in fs]):
130 * fs.append((i, j))
131 * factors[i*j] = fs
132 *
133 * for k, l in sorted(factors.items()):
134 * for v in l:
135 * print("PACK(%s, %s)," % v)
136 */
137 #define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
138 #define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
139 #define UNPACK_OD(val) (((val) & 0xF) + 1)
140 static const u8 factors[] = {
141 PACK(1, 1),
142 PACK(1, 2),
143 PACK(1, 3),
144 PACK(1, 4),
145 PACK(1, 5),
146 PACK(1, 6),
147 PACK(1, 7),
148 PACK(1, 8),
149 PACK(1, 9),
150 PACK(3, 3),
151 PACK(1, 10),
152 PACK(1, 11),
153 PACK(1, 12),
154 PACK(3, 4),
155 PACK(1, 13),
156 PACK(1, 14),
157 PACK(1, 15),
158 PACK(3, 5),
159 PACK(1, 16),
160 PACK(4, 4),
161 PACK(2, 9),
162 PACK(2, 10),
163 PACK(3, 7),
164 PACK(2, 11),
165 PACK(2, 12),
166 PACK(5, 5),
167 PACK(2, 13),
168 PACK(3, 9),
169 PACK(2, 14),
170 PACK(2, 15),
171 PACK(2, 16),
172 PACK(3, 11),
173 PACK(5, 7),
174 PACK(3, 12),
175 PACK(3, 13),
176 PACK(4, 10),
177 PACK(3, 14),
178 PACK(4, 11),
179 PACK(3, 15),
180 PACK(3, 16),
181 PACK(7, 7),
182 PACK(5, 10),
183 PACK(4, 13),
184 PACK(6, 9),
185 PACK(5, 11),
186 PACK(4, 14),
187 PACK(4, 15),
188 PACK(7, 9),
189 PACK(4, 16),
190 PACK(5, 13),
191 PACK(6, 11),
192 PACK(5, 14),
193 PACK(6, 12),
194 PACK(5, 15),
195 PACK(7, 11),
196 PACK(6, 13),
197 PACK(5, 16),
198 PACK(9, 9),
199 PACK(6, 14),
200 PACK(8, 11),
201 PACK(6, 15),
202 PACK(7, 13),
203 PACK(6, 16),
204 PACK(7, 14),
205 PACK(9, 11),
206 PACK(10, 10),
207 PACK(8, 13),
208 PACK(7, 15),
209 PACK(9, 12),
210 PACK(10, 11),
211 PACK(7, 16),
212 PACK(9, 13),
213 PACK(8, 15),
214 PACK(11, 11),
215 PACK(9, 14),
216 PACK(8, 16),
217 PACK(10, 13),
218 PACK(11, 12),
219 PACK(9, 15),
220 PACK(10, 14),
221 PACK(11, 13),
222 PACK(9, 16),
223 PACK(10, 15),
224 PACK(11, 14),
225 PACK(12, 13),
226 PACK(10, 16),
227 PACK(11, 15),
228 PACK(12, 14),
229 PACK(13, 13),
230 PACK(11, 16),
231 PACK(12, 15),
232 PACK(13, 14),
233 PACK(12, 16),
234 PACK(13, 15),
235 PACK(14, 14),
236 PACK(13, 16),
237 PACK(14, 15),
238 PACK(14, 16),
239 PACK(15, 15),
240 PACK(15, 16),
241 PACK(16, 16),
242 };
243
k210_pll_calc_config(u32 rate,u32 rate_in,struct k210_pll_config * best)244 TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
245 struct k210_pll_config *best)
246 {
247 int i;
248 s64 error, best_error;
249 u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
250 u64 max_r;
251 u64 r, f, od;
252
253 /*
254 * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
255 * VCO frequency. These are not the same limits as below because od can
256 * reduce the output frequency by 16.
257 */
258 if (rate > 1750000000 || rate < 21250000)
259 return -EINVAL;
260
261 /* Similar restrictions on the input rate */
262 if (rate_in > 1750000000 || rate_in < 13300000)
263 return -EINVAL;
264
265 ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
266 inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
267 /* Can't increase by more than 64 or reduce by more than 256 */
268 if (rate > rate_in && ratio > (64ULL << 32))
269 return -EINVAL;
270 else if (rate <= rate_in && inv_ratio > (256ULL << 32))
271 return -EINVAL;
272
273 /*
274 * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
275 * MHz. There is no minimum, since the only way to get a higher input
276 * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
277 * cannot output frequencies greater than 1.75 GHz, the minimum would
278 * never be greater than one.
279 */
280 max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
281
282 /* Variables get immediately incremented, so start at -1th iteration */
283 i = -1;
284 f = 0;
285 r = 0;
286 od = 0;
287 best_error = S64_MAX;
288 error = best_error;
289 /* do-while here so we always try at least one ratio */
290 do {
291 /*
292 * Whether we swapped r and od while enforcing frequency limits
293 */
294 bool swapped = false;
295 u64 last_od = od;
296 u64 last_r = r;
297
298 /*
299 * Try the next largest value for f (or r and od) and
300 * recalculate the other parameters based on that
301 */
302 if (rate > rate_in) {
303 /*
304 * Skip factors of the same product if we already tried
305 * out that product
306 */
307 do {
308 i++;
309 r = UNPACK_R(factors[i]);
310 od = UNPACK_OD(factors[i]);
311 } while (i + 1 < ARRAY_SIZE(factors) &&
312 r * od == last_r * last_od);
313
314 /* Round close */
315 f = (r * od * ratio + BIT(31)) >> 32;
316 if (f > 64)
317 f = 64;
318 } else {
319 u64 tmp = ++f * inv_ratio;
320 bool round_up = !!(tmp & BIT(31));
321 u32 goal = (tmp >> 32) + round_up;
322 u32 err, last_err;
323
324 /* Get the next r/od pair in factors */
325 while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
326 i++;
327 r = UNPACK_R(factors[i]);
328 od = UNPACK_OD(factors[i]);
329 }
330
331 /*
332 * This is a case of double rounding. If we rounded up
333 * above, we need to round down (in cases of ties) here.
334 * This prevents off-by-one errors resulting from
335 * choosing X+2 over X when X.Y rounds up to X+1 and
336 * there is no r * od = X+1. For the converse, when X.Y
337 * is rounded down to X, we should choose X+1 over X-1.
338 */
339 err = abs(r * od - goal);
340 last_err = abs(last_r * last_od - goal);
341 if (last_err < err || (round_up && last_err == err)) {
342 i--;
343 r = last_r;
344 od = last_od;
345 }
346 }
347
348 /*
349 * Enforce limits on internal clock frequencies. If we
350 * aren't in spec, try swapping r and od. If everything is
351 * in-spec, calculate the relative error.
352 */
353 while (true) {
354 /*
355 * Whether the intermediate frequencies are out-of-spec
356 */
357 bool out_of_spec = false;
358
359 if (r > max_r) {
360 out_of_spec = true;
361 } else {
362 /*
363 * There is no way to only divide once; we need
364 * to examine the frequency with and without the
365 * effect of od.
366 */
367 u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
368
369 if (vco > 1750000000 || vco < 340000000)
370 out_of_spec = true;
371 }
372
373 if (out_of_spec) {
374 if (!swapped) {
375 u64 tmp = r;
376
377 r = od;
378 od = tmp;
379 swapped = true;
380 continue;
381 } else {
382 /*
383 * Try looking ahead to see if there are
384 * additional factors for the same
385 * product.
386 */
387 if (i + 1 < ARRAY_SIZE(factors)) {
388 u64 new_r, new_od;
389
390 i++;
391 new_r = UNPACK_R(factors[i]);
392 new_od = UNPACK_OD(factors[i]);
393 if (r * od == new_r * new_od) {
394 r = new_r;
395 od = new_od;
396 swapped = false;
397 continue;
398 }
399 i--;
400 }
401 break;
402 }
403 }
404
405 error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
406 /* The lower 16 bits are spurious */
407 error = abs((error - BIT(32))) >> 16;
408
409 if (error < best_error) {
410 best->r = r;
411 best->f = f;
412 best->od = od;
413 best_error = error;
414 }
415 break;
416 }
417 } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
418
419 if (best_error == S64_MAX)
420 return -EINVAL;
421
422 log_debug("best error %lld\n", best_error);
423 return 0;
424 }
425
k210_pll_set_rate(struct clk * clk,ulong rate)426 static ulong k210_pll_set_rate(struct clk *clk, ulong rate)
427 {
428 int err;
429 long long rate_in = clk_get_parent_rate(clk);
430 struct k210_pll_config config = {};
431 struct k210_pll *pll = to_k210_pll(clk);
432 u32 reg;
433
434 if (rate_in < 0)
435 return rate_in;
436
437 log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
438 rate, rate_in);
439 err = k210_pll_calc_config(rate, rate_in, &config);
440 if (err)
441 return err;
442 log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
443
444 /*
445 * Don't use clk_disable as it might not actually disable the pll due to
446 * refcounting
447 */
448 k210_pll_disable(clk);
449
450 reg = readl(pll->reg);
451 reg &= ~K210_PLL_CLKR
452 & ~K210_PLL_CLKF
453 & ~K210_PLL_CLKOD
454 & ~K210_PLL_BWADJ;
455 reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
456 | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
457 | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
458 | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
459 writel(reg, pll->reg);
460
461 err = k210_pll_enable(clk);
462 if (err)
463 return err;
464
465 serial_setbrg();
466 return clk_get_rate(clk);
467 }
468 #endif /* CONFIG_CLK_K210_SET_RATE */
469
k210_pll_get_rate(struct clk * clk)470 static ulong k210_pll_get_rate(struct clk *clk)
471 {
472 long long rate_in = clk_get_parent_rate(clk);
473 struct k210_pll *pll = to_k210_pll(clk);
474 u64 r, f, od;
475 u32 reg = readl(pll->reg);
476
477 if (rate_in < 0 || (reg & K210_PLL_BYPASS))
478 return rate_in;
479
480 if (!(reg & K210_PLL_PWRD))
481 return 0;
482
483 r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
484 f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
485 od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
486
487 return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
488 }
489
490 /*
491 * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
492 * slip before retrying
493 */
k210_pll_waitfor_lock(struct k210_pll * pll)494 static void k210_pll_waitfor_lock(struct k210_pll *pll)
495 {
496 u32 mask = GENMASK(pll->width - 1, 0) << pll->shift;
497
498 while (true) {
499 u32 reg = readl(pll->lock);
500
501 if ((reg & mask) == mask)
502 break;
503
504 reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
505 writel(reg, pll->lock);
506 }
507 }
508
509 /* Adapted from sysctl_pll_enable */
k210_pll_enable(struct clk * clk)510 static int k210_pll_enable(struct clk *clk)
511 {
512 struct k210_pll *pll = to_k210_pll(clk);
513 u32 reg = readl(pll->reg);
514
515 if ((reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
516 !(reg & K210_PLL_RESET))
517 return 0;
518
519 reg |= K210_PLL_PWRD;
520 writel(reg, pll->reg);
521
522 /* Ensure reset is low before asserting it */
523 reg &= ~K210_PLL_RESET;
524 writel(reg, pll->reg);
525 reg |= K210_PLL_RESET;
526 writel(reg, pll->reg);
527 nop();
528 nop();
529 reg &= ~K210_PLL_RESET;
530 writel(reg, pll->reg);
531
532 k210_pll_waitfor_lock(pll);
533
534 reg &= ~K210_PLL_BYPASS;
535 reg |= K210_PLL_EN;
536 writel(reg, pll->reg);
537
538 return 0;
539 }
540
k210_pll_disable(struct clk * clk)541 static int k210_pll_disable(struct clk *clk)
542 {
543 struct k210_pll *pll = to_k210_pll(clk);
544 u32 reg = readl(pll->reg);
545
546 /*
547 * Bypassing before powering off is important so child clocks don't stop
548 * working. This is especially important for pll0, the indirect parent
549 * of the cpu clock.
550 */
551 reg |= K210_PLL_BYPASS;
552 writel(reg, pll->reg);
553
554 reg &= ~K210_PLL_PWRD;
555 reg &= ~K210_PLL_EN;
556 writel(reg, pll->reg);
557 return 0;
558 }
559
560 const struct clk_ops k210_pll_ops = {
561 .get_rate = k210_pll_get_rate,
562 #ifdef CONFIG_CLK_K210_SET_RATE
563 .set_rate = k210_pll_set_rate,
564 #endif
565 .enable = k210_pll_enable,
566 .disable = k210_pll_disable,
567 };
568
k210_register_pll_struct(const char * name,const char * parent_name,struct k210_pll * pll)569 struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
570 struct k210_pll *pll)
571 {
572 int ret;
573 struct clk *clk = &pll->clk;
574
575 ret = clk_register(clk, CLK_K210_PLL, name, parent_name);
576 if (ret)
577 return ERR_PTR(ret);
578 return clk;
579 }
580
581 U_BOOT_DRIVER(k210_pll) = {
582 .name = CLK_K210_PLL,
583 .id = UCLASS_CLK,
584 .ops = &k210_pll_ops,
585 };
586