README
1Overview
2--------
3QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
4development platform, with a complete debugging environment.
5The LS1012AQDS board supports the QorIQ LS1012A processor and is
6optimized to support the high-bandwidth DDR3L memory and
7a full complement of high-speed SerDes ports.
8
9LS1012A SoC Overview
10--------------------
11Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
12SoC overview.
13
14LS1012AQDS board Overview
15-----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - SATA 3.0
20 - DDR Controller
21 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
22 - QSPI Controller
23 - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
24 signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
25 emulator
26 - USB 3.0
27 - One USB 3.0 controller with integrated PHY
28 - One high-speed USB 3.0 port
29 - USB 2.0
30 - One USB 2.0 controller with ULPI interface
31 - Two enhanced secure digital host controllers:
32 - SDHC1 controller can be connected to onboard SDHC connector
33 - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
34 - 2 I2C controllers
35 - One SATA onboard connectors
36 - UART
37 - 5 SAI
38 - One SAI port with audio codec SGTL5000:
39 • Provides MIC bias
40 • Provides headphone and line output
41 - One SAI port terminated at 2x6 header
42 - Three SAI Tx/Rx ports terminated at 2x3 headers
43 - ARM JTAG support
44
45Booting Options
46---------------
47a) QSPI Flash Emu Boot
48b) QSPI Flash 1
49c) QSPI Flash 2
50
51QSPI flash map
52--------------
53Images | Size |QSPI Flash Address
54------------------------------------------
55RCW + PBI | 1MB | 0x4000_0000
56U-boot | 1MB | 0x4010_0000
57U-boot Env | 1MB | 0x4020_0000
58PPA FIT image | 2MB | 0x4050_0000
59Linux ITB | ~53MB | 0x40A0_0000
60