1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <common.h>
4 #include <env.h>
5 #include <malloc.h>
6 #include <net.h>
7 #include <netdev.h>
8 #include <pci.h>
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11
12 #define SROM_DLEVEL 0
13
14 #undef UPDATE_SROM
15
16 /* PCI Registers. */
17 #define PCI_CFDA_PSM 0x43
18
19 #define CFRV_RN 0x000000f0 /* Revision Number */
20
21 #define WAKEUP 0x00 /* Power Saving Wakeup */
22 #define SLEEP 0x80 /* Power Saving Sleep Mode */
23
24 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
25
26 /* Ethernet chip registers. */
27 #define DE4X5_BMR 0x000 /* Bus Mode Register */
28 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
29 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
30 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
31 #define DE4X5_STS 0x028 /* Status Register */
32 #define DE4X5_OMR 0x030 /* Operation Mode Register */
33 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
34 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
35
36 /* Register bits. */
37 #define BMR_SWR 0x00000001 /* Software Reset */
38 #define STS_TS 0x00700000 /* Transmit Process State */
39 #define STS_RS 0x000e0000 /* Receive Process State */
40 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
41 #define OMR_SR 0x00000002 /* Start/Stop Receive */
42 #define OMR_PS 0x00040000 /* Port Select */
43 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
44 #define OMR_PM 0x00000080 /* Pass All Multicast */
45
46 /* Descriptor bits. */
47 #define R_OWN 0x80000000 /* Own Bit */
48 #define RD_RER 0x02000000 /* Receive End Of Ring */
49 #define RD_LS 0x00000100 /* Last Descriptor */
50 #define RD_ES 0x00008000 /* Error Summary */
51 #define TD_TER 0x02000000 /* Transmit End Of Ring */
52 #define T_OWN 0x80000000 /* Own Bit */
53 #define TD_LS 0x40000000 /* Last Segment */
54 #define TD_FS 0x20000000 /* First Segment */
55 #define TD_ES 0x00008000 /* Error Summary */
56 #define TD_SET 0x08000000 /* Setup Packet */
57
58 /* The EEPROM commands include the alway-set leading bit. */
59 #define SROM_WRITE_CMD 5
60 #define SROM_READ_CMD 6
61 #define SROM_ERASE_CMD 7
62
63 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
64 #define SROM_RD 0x00004000 /* Read from Boot ROM */
65 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
66 #define EE_WRITE_0 0x4801
67 #define EE_WRITE_1 0x4805
68 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
69 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
70
71 #define DT_IN 0x00000004 /* Serial Data In */
72 #define DT_CLK 0x00000002 /* Serial ROM Clock */
73 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
74
75 #define POLL_DEMAND 1
76
77 #if defined(CONFIG_E500)
78 #define phys_to_bus(a) (a)
79 #else
80 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
81 #endif
82
83 #define NUM_RX_DESC PKTBUFSRX
84 #define NUM_TX_DESC 1 /* Number of TX descriptors */
85 #define RX_BUFF_SZ PKTSIZE_ALIGN
86
87 #define TOUT_LOOP 1000000
88
89 #define SETUP_FRAME_LEN 192
90
91 struct de4x5_desc {
92 volatile s32 status;
93 u32 des1;
94 u32 buf;
95 u32 next;
96 };
97
98 /* RX and TX descriptor ring */
99 static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
100 static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
101 static int rx_new; /* RX descriptor ring pointer */
102 static int tx_new; /* TX descriptor ring pointer */
103
104 static char rx_ring_size;
105 static char tx_ring_size;
106
dc2114x_inl(struct eth_device * dev,u32 addr)107 static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
108 {
109 return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
110 }
111
dc2114x_outl(struct eth_device * dev,u32 command,u32 addr)112 static void dc2114x_outl(struct eth_device *dev, u32 command, u32 addr)
113 {
114 *(volatile u32 *)(addr + dev->iobase) = cpu_to_le32(command);
115 }
116
reset_de4x5(struct eth_device * dev)117 static void reset_de4x5(struct eth_device *dev)
118 {
119 u32 i;
120
121 i = dc2114x_inl(dev, DE4X5_BMR);
122 mdelay(1);
123 dc2114x_outl(dev, i | BMR_SWR, DE4X5_BMR);
124 mdelay(1);
125 dc2114x_outl(dev, i, DE4X5_BMR);
126 mdelay(1);
127
128 for (i = 0; i < 5; i++) {
129 dc2114x_inl(dev, DE4X5_BMR);
130 mdelay(10);
131 }
132
133 mdelay(1);
134 }
135
start_de4x5(struct eth_device * dev)136 static void start_de4x5(struct eth_device *dev)
137 {
138 u32 omr;
139
140 omr = dc2114x_inl(dev, DE4X5_OMR);
141 omr |= OMR_ST | OMR_SR;
142 dc2114x_outl(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */
143 }
144
stop_de4x5(struct eth_device * dev)145 static void stop_de4x5(struct eth_device *dev)
146 {
147 u32 omr;
148
149 omr = dc2114x_inl(dev, DE4X5_OMR);
150 omr &= ~(OMR_ST | OMR_SR);
151 dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */
152 }
153
154 /* SROM Read and write routines. */
sendto_srom(struct eth_device * dev,u_int command,u_long addr)155 static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
156 {
157 dc2114x_outl(dev, command, addr);
158 udelay(1);
159 }
160
getfrom_srom(struct eth_device * dev,u_long addr)161 static int getfrom_srom(struct eth_device *dev, u_long addr)
162 {
163 u32 tmp = dc2114x_inl(dev, addr);
164
165 udelay(1);
166 return tmp;
167 }
168
169 /* Note: this routine returns extra data bits for size detection. */
do_read_eeprom(struct eth_device * dev,u_long ioaddr,int location,int addr_len)170 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location,
171 int addr_len)
172 {
173 int read_cmd = location | (SROM_READ_CMD << addr_len);
174 unsigned int retval = 0;
175 int i;
176
177 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
178 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
179
180 debug_cond(SROM_DLEVEL >= 1, " EEPROM read at %d ", location);
181
182 /* Shift the read command bits out. */
183 for (i = 4 + addr_len; i >= 0; i--) {
184 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
185
186 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval,
187 ioaddr);
188 udelay(10);
189 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK,
190 ioaddr);
191 udelay(10);
192 debug_cond(SROM_DLEVEL >= 2, "%X",
193 getfrom_srom(dev, ioaddr) & 15);
194 retval = (retval << 1) |
195 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
196 }
197
198 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
199
200 debug_cond(SROM_DLEVEL >= 2, " :%X:", getfrom_srom(dev, ioaddr) & 15);
201
202 for (i = 16; i > 0; i--) {
203 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
204 udelay(10);
205 debug_cond(SROM_DLEVEL >= 2, "%X",
206 getfrom_srom(dev, ioaddr) & 15);
207 retval = (retval << 1) |
208 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
209 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
210 udelay(10);
211 }
212
213 /* Terminate the EEPROM access. */
214 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
215
216 debug_cond(SROM_DLEVEL >= 2, " EEPROM value at %d is %5.5x.\n",
217 location, retval);
218
219 return retval;
220 }
221
222 /*
223 * This executes a generic EEPROM command, typically a write or write
224 * enable. It returns the data output from the EEPROM, and thus may
225 * also be used for reads.
226 */
do_eeprom_cmd(struct eth_device * dev,u_long ioaddr,int cmd,int cmd_len)227 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd,
228 int cmd_len)
229 {
230 unsigned int retval = 0;
231
232 debug_cond(SROM_DLEVEL >= 1, " EEPROM op 0x%x: ", cmd);
233
234 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
235
236 /* Shift the command bits out. */
237 do {
238 short dataval = (cmd & BIT(cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
239
240 sendto_srom(dev, dataval, ioaddr);
241 udelay(10);
242
243 debug_cond(SROM_DLEVEL >= 2, "%X",
244 getfrom_srom(dev, ioaddr) & 15);
245
246 sendto_srom(dev, dataval | DT_CLK, ioaddr);
247 udelay(10);
248 retval = (retval << 1) |
249 !!(getfrom_srom(dev, ioaddr) & EE_DATA_READ);
250 } while (--cmd_len >= 0);
251
252 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
253
254 /* Terminate the EEPROM access. */
255 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
256
257 debug_cond(SROM_DLEVEL >= 1, " EEPROM result is 0x%5.5x.\n", retval);
258
259 return retval;
260 }
261
read_srom(struct eth_device * dev,u_long ioaddr,int index)262 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
263 {
264 int ee_addr_size;
265
266 ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
267
268 return do_eeprom_cmd(dev, ioaddr, 0xffff |
269 (((SROM_READ_CMD << ee_addr_size) | index) << 16),
270 3 + ee_addr_size + 16);
271 }
272
273 #ifdef UPDATE_SROM
write_srom(struct eth_device * dev,u_long ioaddr,int index,int new_value)274 static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
275 int new_value)
276 {
277 unsigned short newval;
278 int ee_addr_size;
279 int i;
280
281 ee_addr_size = (do_read_eeprom(dev, ioaddr, 0xff, 8) & BIT(18)) ? 8 : 6;
282
283 udelay(10 * 1000); /* test-only */
284
285 debug_cond(SROM_DLEVEL >= 1, "ee_addr_size=%d.\n", ee_addr_size);
286 debug_cond(SROM_DLEVEL >= 1,
287 "Writing new entry 0x%4.4x to offset %d.\n",
288 new_value, index);
289
290 /* Enable programming modes. */
291 do_eeprom_cmd(dev, ioaddr, 0x4f << (ee_addr_size - 4),
292 3 + ee_addr_size);
293
294 /* Do the actual write. */
295 do_eeprom_cmd(dev, ioaddr, new_value |
296 (((SROM_WRITE_CMD << ee_addr_size) | index) << 16),
297 3 + ee_addr_size + 16);
298
299 /* Poll for write finished. */
300 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
301 for (i = 0; i < 10000; i++) { /* Typical 2000 ticks */
302 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
303 break;
304 }
305
306 debug_cond(SROM_DLEVEL >= 1, " Write finished after %d ticks.\n", i);
307
308 /* Disable programming. */
309 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size - 4)),
310 3 + ee_addr_size);
311
312 /* And read the result. */
313 newval = do_eeprom_cmd(dev, ioaddr,
314 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
315 | 0xffff, 3 + ee_addr_size + 16);
316
317 debug_cond(SROM_DLEVEL >= 1, " New value at offset %d is %4.4x.\n",
318 index, newval);
319
320 return 1;
321 }
322
update_srom(struct eth_device * dev,bd_t * bis)323 static void update_srom(struct eth_device *dev, bd_t *bis)
324 {
325 static unsigned short eeprom[0x40] = {
326 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
327 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
328 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
329 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
330 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
331 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
332 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
333 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
334 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
335 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
336 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
337 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
338 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
339 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
340 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
341 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
342 };
343 uchar enetaddr[6];
344 int i;
345
346 /* Ethernet Addr... */
347 if (!eth_env_get_enetaddr("ethaddr", enetaddr))
348 return;
349
350 eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
351 eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
352 eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
353
354 for (i = 0; i < 0x40; i++)
355 write_srom(dev, DE4X5_APROM, i, eeprom[i]);
356 }
357 #endif /* UPDATE_SROM */
358
send_setup_frame(struct eth_device * dev,bd_t * bis)359 static void send_setup_frame(struct eth_device *dev, bd_t *bis)
360 {
361 char setup_frame[SETUP_FRAME_LEN];
362 char *pa = &setup_frame[0];
363 int i;
364
365 memset(pa, 0xff, SETUP_FRAME_LEN);
366
367 for (i = 0; i < ETH_ALEN; i++) {
368 *(pa + (i & 1)) = dev->enetaddr[i];
369 if (i & 0x01)
370 pa += 4;
371 }
372
373 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
374 if (i < TOUT_LOOP)
375 continue;
376
377 printf("%s: tx error buffer not ready\n", dev->name);
378 return;
379 }
380
381 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
382 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
383 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
384
385 dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
386
387 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
388 if (i < TOUT_LOOP)
389 continue;
390
391 printf("%s: tx buffer not ready\n", dev->name);
392 return;
393 }
394
395 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
396 printf("TX error status2 = 0x%08X\n",
397 le32_to_cpu(tx_ring[tx_new].status));
398 }
399
400 tx_new = (tx_new + 1) % NUM_TX_DESC;
401 }
402
dc21x4x_send(struct eth_device * dev,void * packet,int length)403 static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
404 {
405 int status = -1;
406 int i;
407
408 if (length <= 0) {
409 printf("%s: bad packet size: %d\n", dev->name, length);
410 goto done;
411 }
412
413 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
414 if (i < TOUT_LOOP)
415 continue;
416
417 printf("%s: tx error buffer not ready\n", dev->name);
418 goto done;
419 }
420
421 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
422 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
423 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
424
425 dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
426
427 for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
428 if (i < TOUT_LOOP)
429 continue;
430
431 printf(".%s: tx buffer not ready\n", dev->name);
432 goto done;
433 }
434
435 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
436 tx_ring[tx_new].status = 0x0;
437 goto done;
438 }
439
440 status = length;
441
442 done:
443 tx_new = (tx_new + 1) % NUM_TX_DESC;
444 return status;
445 }
446
dc21x4x_recv(struct eth_device * dev)447 static int dc21x4x_recv(struct eth_device *dev)
448 {
449 int length = 0;
450 u32 status;
451
452 while (true) {
453 status = le32_to_cpu(rx_ring[rx_new].status);
454
455 if (status & R_OWN)
456 break;
457
458 if (status & RD_LS) {
459 /* Valid frame status. */
460 if (status & RD_ES) {
461 /* There was an error. */
462 printf("RX error status = 0x%08X\n", status);
463 } else {
464 /* A valid frame received. */
465 length = (le32_to_cpu(rx_ring[rx_new].status)
466 >> 16);
467
468 /* Pass the packet up to the protocol layers */
469 net_process_received_packet
470 (net_rx_packets[rx_new], length - 4);
471 }
472
473 /*
474 * Change buffer ownership for this frame,
475 * back to the adapter.
476 */
477 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
478 }
479
480 /* Update entry information. */
481 rx_new = (rx_new + 1) % rx_ring_size;
482 }
483
484 return length;
485 }
486
dc21x4x_init(struct eth_device * dev,bd_t * bis)487 static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
488 {
489 int i;
490 int devbusfn = (int)dev->priv;
491
492 /* Ensure we're not sleeping. */
493 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
494
495 reset_de4x5(dev);
496
497 if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
498 printf("Error: Cannot reset ethernet controller.\n");
499 return -1;
500 }
501
502 dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
503
504 for (i = 0; i < NUM_RX_DESC; i++) {
505 rx_ring[i].status = cpu_to_le32(R_OWN);
506 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
507 rx_ring[i].buf =
508 cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
509 rx_ring[i].next = 0;
510 }
511
512 for (i = 0; i < NUM_TX_DESC; i++) {
513 tx_ring[i].status = 0;
514 tx_ring[i].des1 = 0;
515 tx_ring[i].buf = 0;
516 tx_ring[i].next = 0;
517 }
518
519 rx_ring_size = NUM_RX_DESC;
520 tx_ring_size = NUM_TX_DESC;
521
522 /* Write the end of list marker to the descriptor lists. */
523 rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
524 tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
525
526 /* Tell the adapter where the TX/RX rings are located. */
527 dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
528 dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
529
530 start_de4x5(dev);
531
532 tx_new = 0;
533 rx_new = 0;
534
535 send_setup_frame(dev, bis);
536
537 return 0;
538 }
539
dc21x4x_halt(struct eth_device * dev)540 static void dc21x4x_halt(struct eth_device *dev)
541 {
542 int devbusfn = (int)dev->priv;
543
544 stop_de4x5(dev);
545 dc2114x_outl(dev, 0, DE4X5_SICR);
546
547 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
548 }
549
read_hw_addr(struct eth_device * dev,bd_t * bis)550 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
551 {
552 u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
553 int i, j = 0;
554
555 for (i = 0; i < (ETH_ALEN >> 1); i++) {
556 tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
557 *p = le16_to_cpu(tmp);
558 j += *p++;
559 }
560
561 if (!j || j == 0x2fffd) {
562 memset(dev->enetaddr, 0, ETH_ALEN);
563 debug("Warning: can't read HW address from SROM.\n");
564 #ifdef UPDATE_SROM
565 update_srom(dev, bis);
566 #endif
567 }
568 }
569
570 static struct pci_device_id supported[] = {
571 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
572 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
573 { }
574 };
575
dc21x4x_initialize(bd_t * bis)576 int dc21x4x_initialize(bd_t *bis)
577 {
578 struct eth_device *dev;
579 unsigned short status;
580 unsigned char timer;
581 unsigned int iobase;
582 int card_number = 0;
583 pci_dev_t devbusfn;
584 unsigned int cfrv;
585 int idx = 0;
586
587 while (1) {
588 devbusfn = pci_find_devices(supported, idx++);
589 if (devbusfn == -1)
590 break;
591
592 /* Get the chip configuration revision register. */
593 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
594
595 if ((cfrv & CFRV_RN) < DC2114x_BRK) {
596 printf("Error: The chip is not DC21143.\n");
597 continue;
598 }
599
600 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
601 status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
602 pci_write_config_word(devbusfn, PCI_COMMAND, status);
603
604 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
605 if (!(status & PCI_COMMAND_MEMORY)) {
606 printf("Error: Can not enable MEMORY access.\n");
607 continue;
608 }
609
610 if (!(status & PCI_COMMAND_MASTER)) {
611 printf("Error: Can not enable Bus Mastering.\n");
612 continue;
613 }
614
615 /* Check the latency timer for values >= 0x60. */
616 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
617
618 if (timer < 0x60) {
619 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
620 0x60);
621 }
622
623 /* read BAR for memory space access */
624 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
625 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
626 debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
627
628 dev = (struct eth_device *)malloc(sizeof(*dev));
629 if (!dev) {
630 printf("Can not allocalte memory of dc21x4x\n");
631 break;
632 }
633
634 memset(dev, 0, sizeof(*dev));
635
636 sprintf(dev->name, "dc21x4x#%d", card_number);
637
638 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
639 dev->priv = (void *)devbusfn;
640 dev->init = dc21x4x_init;
641 dev->halt = dc21x4x_halt;
642 dev->send = dc21x4x_send;
643 dev->recv = dc21x4x_recv;
644
645 /* Ensure we're not sleeping. */
646 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
647
648 udelay(10 * 1000);
649
650 read_hw_addr(dev, bis);
651
652 eth_register(dev);
653
654 card_number++;
655 }
656
657 return card_number;
658 }
659