1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <cpu_func.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <generic-phy.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <memalign.h>
16 #include <phys2bus.h>
17 #include <usb.h>
18 #include <usbroothubdes.h>
19 #include <wait_bit.h>
20 #include <asm/cache.h>
21 #include <asm/io.h>
22 #include <dm/device_compat.h>
23 #include <linux/delay.h>
24 #include <power/regulator.h>
25 #include <reset.h>
26
27 #include "dwc2.h"
28
29 /* Use only HC channel 0. */
30 #define DWC2_HC_CHANNEL 0
31
32 #define DWC2_STATUS_BUF_SIZE 64
33 #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
34
35 #define MAX_DEVICE 16
36 #define MAX_ENDPOINT 16
37
38 struct dwc2_priv {
39 #if CONFIG_IS_ENABLED(DM_USB)
40 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
41 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
42 #ifdef CONFIG_DM_REGULATOR
43 struct udevice *vbus_supply;
44 #endif
45 struct phy phy;
46 struct clk_bulk clks;
47 #else
48 uint8_t *aligned_buffer;
49 uint8_t *status_buffer;
50 #endif
51 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
52 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
53 struct dwc2_core_regs *regs;
54 int root_hub_devnum;
55 bool ext_vbus;
56 /*
57 * The hnp/srp capability must be disabled if the platform
58 * does't support hnp/srp. Otherwise the force mode can't work.
59 */
60 bool hnp_srp_disable;
61 bool oc_disable;
62
63 struct reset_ctl_bulk resets;
64 };
65
66 #if !CONFIG_IS_ENABLED(DM_USB)
67 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
68 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
69 ARCH_DMA_MINALIGN);
70 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
71 ARCH_DMA_MINALIGN);
72
73 static struct dwc2_priv local;
74 #endif
75
76 /*
77 * DWC2 IP interface
78 */
79
80 /*
81 * Initializes the FSLSPClkSel field of the HCFG register
82 * depending on the PHY type.
83 */
init_fslspclksel(struct dwc2_core_regs * regs)84 static void init_fslspclksel(struct dwc2_core_regs *regs)
85 {
86 uint32_t phyclk;
87
88 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
89 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
90 #else
91 /* High speed PHY running at full speed or high speed */
92 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
93 #endif
94
95 #ifdef CONFIG_DWC2_ULPI_FS_LS
96 uint32_t hwcfg2 = readl(®s->ghwcfg2);
97 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
98 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
99 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
100 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
101
102 if (hval == 2 && fval == 1)
103 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
104 #endif
105
106 clrsetbits_le32(®s->host_regs.hcfg,
107 DWC2_HCFG_FSLSPCLKSEL_MASK,
108 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
109 }
110
111 /*
112 * Flush a Tx FIFO.
113 *
114 * @param regs Programming view of DWC_otg controller.
115 * @param num Tx FIFO to flush.
116 */
dwc_otg_flush_tx_fifo(struct dwc2_core_regs * regs,const int num)117 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
118 {
119 int ret;
120
121 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
122 ®s->grstctl);
123 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
124 false, 1000, false);
125 if (ret)
126 dev_info(dev, "%s: Timeout!\n", __func__);
127
128 /* Wait for 3 PHY Clocks */
129 udelay(1);
130 }
131
132 /*
133 * Flush Rx FIFO.
134 *
135 * @param regs Programming view of DWC_otg controller.
136 */
dwc_otg_flush_rx_fifo(struct dwc2_core_regs * regs)137 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
138 {
139 int ret;
140
141 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
142 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
143 false, 1000, false);
144 if (ret)
145 dev_info(dev, "%s: Timeout!\n", __func__);
146
147 /* Wait for 3 PHY Clocks */
148 udelay(1);
149 }
150
151 /*
152 * Do core a soft reset of the core. Be careful with this because it
153 * resets all the internal state machines of the core.
154 */
dwc_otg_core_reset(struct dwc2_core_regs * regs)155 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
156 {
157 int ret;
158
159 /* Wait for AHB master IDLE state. */
160 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
161 true, 1000, false);
162 if (ret)
163 dev_info(dev, "%s: Timeout!\n", __func__);
164
165 /* Core Soft Reset */
166 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
167 ret = wait_for_bit_le32(®s->grstctl, DWC2_GRSTCTL_CSFTRST,
168 false, 1000, false);
169 if (ret)
170 dev_info(dev, "%s: Timeout!\n", __func__);
171
172 /*
173 * Wait for core to come out of reset.
174 * NOTE: This long sleep is _very_ important, otherwise the core will
175 * not stay in host mode after a connector ID change!
176 */
177 mdelay(100);
178 }
179
180 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
dwc_vbus_supply_init(struct udevice * dev)181 static int dwc_vbus_supply_init(struct udevice *dev)
182 {
183 struct dwc2_priv *priv = dev_get_priv(dev);
184 int ret;
185
186 ret = device_get_supply_regulator(dev, "vbus-supply",
187 &priv->vbus_supply);
188 if (ret) {
189 debug("%s: No vbus supply\n", dev->name);
190 return 0;
191 }
192
193 ret = regulator_set_enable(priv->vbus_supply, true);
194 if (ret) {
195 dev_err(dev, "Error enabling vbus supply\n");
196 return ret;
197 }
198
199 return 0;
200 }
201
dwc_vbus_supply_exit(struct udevice * dev)202 static int dwc_vbus_supply_exit(struct udevice *dev)
203 {
204 struct dwc2_priv *priv = dev_get_priv(dev);
205 int ret;
206
207 if (priv->vbus_supply) {
208 ret = regulator_set_enable(priv->vbus_supply, false);
209 if (ret) {
210 dev_err(dev, "Error disabling vbus supply\n");
211 return ret;
212 }
213 }
214
215 return 0;
216 }
217 #else
dwc_vbus_supply_init(struct udevice * dev)218 static int dwc_vbus_supply_init(struct udevice *dev)
219 {
220 return 0;
221 }
222
223 #if CONFIG_IS_ENABLED(DM_USB)
dwc_vbus_supply_exit(struct udevice * dev)224 static int dwc_vbus_supply_exit(struct udevice *dev)
225 {
226 return 0;
227 }
228 #endif
229 #endif
230
231 /*
232 * This function initializes the DWC_otg controller registers for
233 * host mode.
234 *
235 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
236 * request queues. Host channels are reset to ensure that they are ready for
237 * performing transfers.
238 *
239 * @param dev USB Device (NULL if driver model is not being used)
240 * @param regs Programming view of DWC_otg controller
241 *
242 */
dwc_otg_core_host_init(struct udevice * dev,struct dwc2_core_regs * regs)243 static void dwc_otg_core_host_init(struct udevice *dev,
244 struct dwc2_core_regs *regs)
245 {
246 uint32_t nptxfifosize = 0;
247 uint32_t ptxfifosize = 0;
248 uint32_t hprt0 = 0;
249 int i, ret, num_channels;
250
251 /* Restart the Phy Clock */
252 writel(0, ®s->pcgcctl);
253
254 /* Initialize Host Configuration Register */
255 init_fslspclksel(regs);
256 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
257 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
258 #endif
259
260 /* Configure data FIFO sizes */
261 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
262 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
263 /* Rx FIFO */
264 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
265
266 /* Non-periodic Tx FIFO */
267 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
268 DWC2_FIFOSIZE_DEPTH_OFFSET;
269 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
270 DWC2_FIFOSIZE_STARTADDR_OFFSET;
271 writel(nptxfifosize, ®s->gnptxfsiz);
272
273 /* Periodic Tx FIFO */
274 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
275 DWC2_FIFOSIZE_DEPTH_OFFSET;
276 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
277 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
278 DWC2_FIFOSIZE_STARTADDR_OFFSET;
279 writel(ptxfifosize, ®s->hptxfsiz);
280 }
281 #endif
282
283 /* Clear Host Set HNP Enable in the OTG Control Register */
284 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
285
286 /* Make sure the FIFOs are flushed. */
287 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
288 dwc_otg_flush_rx_fifo(regs);
289
290 /* Flush out any leftover queued requests. */
291 num_channels = readl(®s->ghwcfg2);
292 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
293 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
294 num_channels += 1;
295
296 for (i = 0; i < num_channels; i++)
297 clrsetbits_le32(®s->hc_regs[i].hcchar,
298 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
299 DWC2_HCCHAR_CHDIS);
300
301 /* Halt all channels to put them into a known state. */
302 for (i = 0; i < num_channels; i++) {
303 clrsetbits_le32(®s->hc_regs[i].hcchar,
304 DWC2_HCCHAR_EPDIR,
305 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
306 ret = wait_for_bit_le32(®s->hc_regs[i].hcchar,
307 DWC2_HCCHAR_CHEN, false, 1000, false);
308 if (ret)
309 dev_info("%s: Timeout!\n", __func__);
310 }
311
312 /* Turn on the vbus power. */
313 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
314 hprt0 = readl(®s->hprt0);
315 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
316 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
317 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
318 hprt0 |= DWC2_HPRT0_PRTPWR;
319 writel(hprt0, ®s->hprt0);
320 }
321 }
322
323 if (dev)
324 dwc_vbus_supply_init(dev);
325 }
326
327 /*
328 * This function initializes the DWC_otg controller registers and
329 * prepares the core for device mode or host mode operation.
330 *
331 * @param regs Programming view of the DWC_otg controller
332 */
dwc_otg_core_init(struct dwc2_priv * priv)333 static void dwc_otg_core_init(struct dwc2_priv *priv)
334 {
335 struct dwc2_core_regs *regs = priv->regs;
336 uint32_t ahbcfg = 0;
337 uint32_t usbcfg = 0;
338 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
339
340 /* Common Initialization */
341 usbcfg = readl(®s->gusbcfg);
342
343 /* Program the ULPI External VBUS bit if needed */
344 if (priv->ext_vbus) {
345 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
346 if (!priv->oc_disable) {
347 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
348 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
349 }
350 } else {
351 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
352 }
353
354 /* Set external TS Dline pulsing */
355 #ifdef CONFIG_DWC2_TS_DLINE
356 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
357 #else
358 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
359 #endif
360 writel(usbcfg, ®s->gusbcfg);
361
362 /* Reset the Controller */
363 dwc_otg_core_reset(regs);
364
365 /*
366 * This programming sequence needs to happen in FS mode before
367 * any other programming occurs
368 */
369 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
370 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
371 /* If FS mode with FS PHY */
372 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
373
374 /* Reset after a PHY select */
375 dwc_otg_core_reset(regs);
376
377 /*
378 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
379 * Also do this on HNP Dev/Host mode switches (done in dev_init
380 * and host_init).
381 */
382 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
383 init_fslspclksel(regs);
384
385 #ifdef CONFIG_DWC2_I2C_ENABLE
386 /* Program GUSBCFG.OtgUtmifsSel to I2C */
387 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
388
389 /* Program GI2CCTL.I2CEn */
390 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
391 DWC2_GI2CCTL_I2CDEVADDR_MASK,
392 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
393 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
394 #endif
395
396 #else
397 /* High speed PHY. */
398
399 /*
400 * HS PHY parameters. These parameters are preserved during
401 * soft reset so only program the first time. Do a soft reset
402 * immediately after setting phyif.
403 */
404 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
405 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
406
407 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
408 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
409 usbcfg |= DWC2_GUSBCFG_DDRSEL;
410 #else
411 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
412 #endif
413 } else { /* UTMI+ interface */
414 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
415 usbcfg |= DWC2_GUSBCFG_PHYIF;
416 #endif
417 }
418
419 writel(usbcfg, ®s->gusbcfg);
420
421 /* Reset after setting the PHY parameters */
422 dwc_otg_core_reset(regs);
423 #endif
424
425 usbcfg = readl(®s->gusbcfg);
426 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
427 #ifdef CONFIG_DWC2_ULPI_FS_LS
428 uint32_t hwcfg2 = readl(®s->ghwcfg2);
429 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
430 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
431 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
432 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
433 if (hval == 2 && fval == 1) {
434 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
435 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
436 }
437 #endif
438 if (priv->hnp_srp_disable)
439 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
440
441 writel(usbcfg, ®s->gusbcfg);
442
443 /* Program the GAHBCFG Register. */
444 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
445 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
446 break;
447 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
448 while (brst_sz > 1) {
449 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
450 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
451 brst_sz >>= 1;
452 }
453
454 #ifdef CONFIG_DWC2_DMA_ENABLE
455 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
456 #endif
457 break;
458
459 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
460 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
461 #ifdef CONFIG_DWC2_DMA_ENABLE
462 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
463 #endif
464 break;
465 }
466
467 writel(ahbcfg, ®s->gahbcfg);
468
469 /* Program the capabilities in GUSBCFG Register */
470 usbcfg = 0;
471
472 if (!priv->hnp_srp_disable)
473 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
474 #ifdef CONFIG_DWC2_IC_USB_CAP
475 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
476 #endif
477
478 setbits_le32(®s->gusbcfg, usbcfg);
479 }
480
481 /*
482 * Prepares a host channel for transferring packets to/from a specific
483 * endpoint. The HCCHARn register is set up with the characteristics specified
484 * in _hc. Host channel interrupts that may need to be serviced while this
485 * transfer is in progress are enabled.
486 *
487 * @param regs Programming view of DWC_otg controller
488 * @param hc Information needed to initialize the host channel
489 */
dwc_otg_hc_init(struct dwc2_core_regs * regs,uint8_t hc_num,struct usb_device * dev,uint8_t dev_addr,uint8_t ep_num,uint8_t ep_is_in,uint8_t ep_type,uint16_t max_packet)490 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
491 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
492 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
493 {
494 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
495 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
496 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
497 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
498 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
499 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
500
501 if (dev->speed == USB_SPEED_LOW)
502 hcchar |= DWC2_HCCHAR_LSPDDEV;
503
504 /*
505 * Program the HCCHARn register with the endpoint characteristics
506 * for the current transfer.
507 */
508 writel(hcchar, &hc_regs->hcchar);
509
510 /* Program the HCSPLIT register, default to no SPLIT */
511 writel(0, &hc_regs->hcsplt);
512 }
513
dwc_otg_hc_init_split(struct dwc2_hc_regs * hc_regs,uint8_t hub_devnum,uint8_t hub_port)514 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
515 uint8_t hub_devnum, uint8_t hub_port)
516 {
517 uint32_t hcsplt = 0;
518
519 hcsplt = DWC2_HCSPLT_SPLTENA;
520 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
521 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
522
523 /* Program the HCSPLIT register for SPLITs */
524 writel(hcsplt, &hc_regs->hcsplt);
525 }
526
527 /*
528 * DWC2 to USB API interface
529 */
530 /* Direction: In ; Request: Status */
dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs * regs,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)531 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
532 struct usb_device *dev, void *buffer,
533 int txlen, struct devrequest *cmd)
534 {
535 uint32_t hprt0 = 0;
536 uint32_t port_status = 0;
537 uint32_t port_change = 0;
538 int len = 0;
539 int stat = 0;
540
541 switch (cmd->requesttype & ~USB_DIR_IN) {
542 case 0:
543 *(uint16_t *)buffer = cpu_to_le16(1);
544 len = 2;
545 break;
546 case USB_RECIP_INTERFACE:
547 case USB_RECIP_ENDPOINT:
548 *(uint16_t *)buffer = cpu_to_le16(0);
549 len = 2;
550 break;
551 case USB_TYPE_CLASS:
552 *(uint32_t *)buffer = cpu_to_le32(0);
553 len = 4;
554 break;
555 case USB_RECIP_OTHER | USB_TYPE_CLASS:
556 hprt0 = readl(®s->hprt0);
557 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
558 port_status |= USB_PORT_STAT_CONNECTION;
559 if (hprt0 & DWC2_HPRT0_PRTENA)
560 port_status |= USB_PORT_STAT_ENABLE;
561 if (hprt0 & DWC2_HPRT0_PRTSUSP)
562 port_status |= USB_PORT_STAT_SUSPEND;
563 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
564 port_status |= USB_PORT_STAT_OVERCURRENT;
565 if (hprt0 & DWC2_HPRT0_PRTRST)
566 port_status |= USB_PORT_STAT_RESET;
567 if (hprt0 & DWC2_HPRT0_PRTPWR)
568 port_status |= USB_PORT_STAT_POWER;
569
570 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
571 port_status |= USB_PORT_STAT_LOW_SPEED;
572 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
573 DWC2_HPRT0_PRTSPD_HIGH)
574 port_status |= USB_PORT_STAT_HIGH_SPEED;
575
576 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
577 port_change |= USB_PORT_STAT_C_ENABLE;
578 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
579 port_change |= USB_PORT_STAT_C_CONNECTION;
580 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
581 port_change |= USB_PORT_STAT_C_OVERCURRENT;
582
583 *(uint32_t *)buffer = cpu_to_le32(port_status |
584 (port_change << 16));
585 len = 4;
586 break;
587 default:
588 puts("unsupported root hub command\n");
589 stat = USB_ST_STALLED;
590 }
591
592 dev->act_len = min(len, txlen);
593 dev->status = stat;
594
595 return stat;
596 }
597
598 /* Direction: In ; Request: Descriptor */
dwc_otg_submit_rh_msg_in_descriptor(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)599 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
600 void *buffer, int txlen,
601 struct devrequest *cmd)
602 {
603 unsigned char data[32];
604 uint32_t dsc;
605 int len = 0;
606 int stat = 0;
607 uint16_t wValue = cpu_to_le16(cmd->value);
608 uint16_t wLength = cpu_to_le16(cmd->length);
609
610 switch (cmd->requesttype & ~USB_DIR_IN) {
611 case 0:
612 switch (wValue & 0xff00) {
613 case 0x0100: /* device descriptor */
614 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
615 memcpy(buffer, root_hub_dev_des, len);
616 break;
617 case 0x0200: /* configuration descriptor */
618 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
619 memcpy(buffer, root_hub_config_des, len);
620 break;
621 case 0x0300: /* string descriptors */
622 switch (wValue & 0xff) {
623 case 0x00:
624 len = min3(txlen, (int)sizeof(root_hub_str_index0),
625 (int)wLength);
626 memcpy(buffer, root_hub_str_index0, len);
627 break;
628 case 0x01:
629 len = min3(txlen, (int)sizeof(root_hub_str_index1),
630 (int)wLength);
631 memcpy(buffer, root_hub_str_index1, len);
632 break;
633 }
634 break;
635 default:
636 stat = USB_ST_STALLED;
637 }
638 break;
639
640 case USB_TYPE_CLASS:
641 /* Root port config, set 1 port and nothing else. */
642 dsc = 0x00000001;
643
644 data[0] = 9; /* min length; */
645 data[1] = 0x29;
646 data[2] = dsc & RH_A_NDP;
647 data[3] = 0;
648 if (dsc & RH_A_PSM)
649 data[3] |= 0x1;
650 if (dsc & RH_A_NOCP)
651 data[3] |= 0x10;
652 else if (dsc & RH_A_OCPM)
653 data[3] |= 0x8;
654
655 /* corresponds to data[4-7] */
656 data[5] = (dsc & RH_A_POTPGT) >> 24;
657 data[7] = dsc & RH_B_DR;
658 if (data[2] < 7) {
659 data[8] = 0xff;
660 } else {
661 data[0] += 2;
662 data[8] = (dsc & RH_B_DR) >> 8;
663 data[9] = 0xff;
664 data[10] = data[9];
665 }
666
667 len = min3(txlen, (int)data[0], (int)wLength);
668 memcpy(buffer, data, len);
669 break;
670 default:
671 puts("unsupported root hub command\n");
672 stat = USB_ST_STALLED;
673 }
674
675 dev->act_len = min(len, txlen);
676 dev->status = stat;
677
678 return stat;
679 }
680
681 /* Direction: In ; Request: Configuration */
dwc_otg_submit_rh_msg_in_configuration(struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)682 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
683 void *buffer, int txlen,
684 struct devrequest *cmd)
685 {
686 int len = 0;
687 int stat = 0;
688
689 switch (cmd->requesttype & ~USB_DIR_IN) {
690 case 0:
691 *(uint8_t *)buffer = 0x01;
692 len = 1;
693 break;
694 default:
695 puts("unsupported root hub command\n");
696 stat = USB_ST_STALLED;
697 }
698
699 dev->act_len = min(len, txlen);
700 dev->status = stat;
701
702 return stat;
703 }
704
705 /* Direction: In */
dwc_otg_submit_rh_msg_in(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)706 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
707 struct usb_device *dev, void *buffer,
708 int txlen, struct devrequest *cmd)
709 {
710 switch (cmd->request) {
711 case USB_REQ_GET_STATUS:
712 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
713 txlen, cmd);
714 case USB_REQ_GET_DESCRIPTOR:
715 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
716 txlen, cmd);
717 case USB_REQ_GET_CONFIGURATION:
718 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
719 txlen, cmd);
720 default:
721 puts("unsupported root hub command\n");
722 return USB_ST_STALLED;
723 }
724 }
725
726 /* Direction: Out */
dwc_otg_submit_rh_msg_out(struct dwc2_priv * priv,struct usb_device * dev,void * buffer,int txlen,struct devrequest * cmd)727 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
728 struct usb_device *dev,
729 void *buffer, int txlen,
730 struct devrequest *cmd)
731 {
732 struct dwc2_core_regs *regs = priv->regs;
733 int len = 0;
734 int stat = 0;
735 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
736 uint16_t wValue = cpu_to_le16(cmd->value);
737
738 switch (bmrtype_breq & ~USB_DIR_IN) {
739 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
740 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
741 break;
742
743 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
744 switch (wValue) {
745 case USB_PORT_FEAT_C_CONNECTION:
746 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
747 break;
748 }
749 break;
750
751 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
752 switch (wValue) {
753 case USB_PORT_FEAT_SUSPEND:
754 break;
755
756 case USB_PORT_FEAT_RESET:
757 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
758 DWC2_HPRT0_PRTCONNDET |
759 DWC2_HPRT0_PRTENCHNG |
760 DWC2_HPRT0_PRTOVRCURRCHNG,
761 DWC2_HPRT0_PRTRST);
762 mdelay(50);
763 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
764 break;
765
766 case USB_PORT_FEAT_POWER:
767 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
768 DWC2_HPRT0_PRTCONNDET |
769 DWC2_HPRT0_PRTENCHNG |
770 DWC2_HPRT0_PRTOVRCURRCHNG,
771 DWC2_HPRT0_PRTRST);
772 break;
773
774 case USB_PORT_FEAT_ENABLE:
775 break;
776 }
777 break;
778 case (USB_REQ_SET_ADDRESS << 8):
779 priv->root_hub_devnum = wValue;
780 break;
781 case (USB_REQ_SET_CONFIGURATION << 8):
782 break;
783 default:
784 puts("unsupported root hub command\n");
785 stat = USB_ST_STALLED;
786 }
787
788 len = min(len, txlen);
789
790 dev->act_len = len;
791 dev->status = stat;
792
793 return stat;
794 }
795
dwc_otg_submit_rh_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int txlen,struct devrequest * cmd)796 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
797 unsigned long pipe, void *buffer, int txlen,
798 struct devrequest *cmd)
799 {
800 int stat = 0;
801
802 if (usb_pipeint(pipe)) {
803 puts("Root-Hub submit IRQ: NOT implemented\n");
804 return 0;
805 }
806
807 if (cmd->requesttype & USB_DIR_IN)
808 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
809 else
810 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
811
812 mdelay(1);
813
814 return stat;
815 }
816
wait_for_chhltd(struct dwc2_hc_regs * hc_regs,uint32_t * sub,u8 * toggle)817 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
818 {
819 int ret;
820 uint32_t hcint, hctsiz;
821
822 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
823 2000, false);
824 if (ret)
825 return ret;
826
827 hcint = readl(&hc_regs->hcint);
828 hctsiz = readl(&hc_regs->hctsiz);
829 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
830 DWC2_HCTSIZ_XFERSIZE_OFFSET;
831 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
832
833 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
834 *toggle);
835
836 if (hcint & DWC2_HCINT_XFERCOMP)
837 return 0;
838
839 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
840 return -EAGAIN;
841
842 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
843 return -EINVAL;
844 }
845
846 static int dwc2_eptype[] = {
847 DWC2_HCCHAR_EPTYPE_ISOC,
848 DWC2_HCCHAR_EPTYPE_INTR,
849 DWC2_HCCHAR_EPTYPE_CONTROL,
850 DWC2_HCCHAR_EPTYPE_BULK,
851 };
852
transfer_chunk(struct dwc2_hc_regs * hc_regs,void * aligned_buffer,u8 * pid,int in,void * buffer,int num_packets,int xfer_len,int * actual_len,int odd_frame)853 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
854 u8 *pid, int in, void *buffer, int num_packets,
855 int xfer_len, int *actual_len, int odd_frame)
856 {
857 int ret = 0;
858 uint32_t sub;
859
860 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
861 *pid, xfer_len, num_packets);
862
863 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
864 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
865 (*pid << DWC2_HCTSIZ_PID_OFFSET),
866 &hc_regs->hctsiz);
867
868 if (xfer_len) {
869 if (in) {
870 invalidate_dcache_range(
871 (uintptr_t)aligned_buffer,
872 (uintptr_t)aligned_buffer +
873 roundup(xfer_len, ARCH_DMA_MINALIGN));
874 } else {
875 memcpy(aligned_buffer, buffer, xfer_len);
876 flush_dcache_range(
877 (uintptr_t)aligned_buffer,
878 (uintptr_t)aligned_buffer +
879 roundup(xfer_len, ARCH_DMA_MINALIGN));
880 }
881 }
882
883 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
884
885 /* Clear old interrupt conditions for this host channel. */
886 writel(0x3fff, &hc_regs->hcint);
887
888 /* Set host channel enable after all other setup is complete. */
889 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
890 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
891 DWC2_HCCHAR_ODDFRM,
892 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
893 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
894 DWC2_HCCHAR_CHEN);
895
896 ret = wait_for_chhltd(hc_regs, &sub, pid);
897 if (ret < 0)
898 return ret;
899
900 if (in) {
901 xfer_len -= sub;
902
903 invalidate_dcache_range((unsigned long)aligned_buffer,
904 (unsigned long)aligned_buffer +
905 roundup(xfer_len, ARCH_DMA_MINALIGN));
906
907 memcpy(buffer, aligned_buffer, xfer_len);
908 }
909 *actual_len = xfer_len;
910
911 return ret;
912 }
913
chunk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,u8 * pid,int in,void * buffer,int len)914 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
915 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
916 {
917 struct dwc2_core_regs *regs = priv->regs;
918 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
919 struct dwc2_host_regs *host_regs = ®s->host_regs;
920 int devnum = usb_pipedevice(pipe);
921 int ep = usb_pipeendpoint(pipe);
922 int max = usb_maxpacket(dev, pipe);
923 int eptype = dwc2_eptype[usb_pipetype(pipe)];
924 int done = 0;
925 int ret = 0;
926 int do_split = 0;
927 int complete_split = 0;
928 uint32_t xfer_len;
929 uint32_t num_packets;
930 int stop_transfer = 0;
931 uint32_t max_xfer_len;
932 int ssplit_frame_num = 0;
933
934 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
935 in, len);
936
937 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
938 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
939 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
940 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
941 max_xfer_len = DWC2_DATA_BUF_SIZE;
942
943 /* Make sure that max_xfer_len is a multiple of max packet size. */
944 num_packets = max_xfer_len / max;
945 max_xfer_len = num_packets * max;
946
947 /* Initialize channel */
948 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
949 eptype, max);
950
951 /* Check if the target is a FS/LS device behind a HS hub */
952 if (dev->speed != USB_SPEED_HIGH) {
953 uint8_t hub_addr;
954 uint8_t hub_port;
955 uint32_t hprt0 = readl(®s->hprt0);
956 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
957 DWC2_HPRT0_PRTSPD_HIGH) {
958 usb_find_usb2_hub_address_port(dev, &hub_addr,
959 &hub_port);
960 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
961
962 do_split = 1;
963 num_packets = 1;
964 max_xfer_len = max;
965 }
966 }
967
968 do {
969 int actual_len = 0;
970 uint32_t hcint;
971 int odd_frame = 0;
972 xfer_len = len - done;
973
974 if (xfer_len > max_xfer_len)
975 xfer_len = max_xfer_len;
976 else if (xfer_len > max)
977 num_packets = (xfer_len + max - 1) / max;
978 else
979 num_packets = 1;
980
981 if (complete_split)
982 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
983 else if (do_split)
984 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
985
986 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
987 int uframe_num = readl(&host_regs->hfnum);
988 if (!(uframe_num & 0x1))
989 odd_frame = 1;
990 }
991
992 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
993 in, (char *)buffer + done, num_packets,
994 xfer_len, &actual_len, odd_frame);
995
996 hcint = readl(&hc_regs->hcint);
997 if (complete_split) {
998 stop_transfer = 0;
999 if (hcint & DWC2_HCINT_NYET) {
1000 ret = 0;
1001 int frame_num = DWC2_HFNUM_MAX_FRNUM &
1002 readl(&host_regs->hfnum);
1003 if (((frame_num - ssplit_frame_num) &
1004 DWC2_HFNUM_MAX_FRNUM) > 4)
1005 ret = -EAGAIN;
1006 } else
1007 complete_split = 0;
1008 } else if (do_split) {
1009 if (hcint & DWC2_HCINT_ACK) {
1010 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1011 readl(&host_regs->hfnum);
1012 ret = 0;
1013 complete_split = 1;
1014 }
1015 }
1016
1017 if (ret)
1018 break;
1019
1020 if (actual_len < xfer_len)
1021 stop_transfer = 1;
1022
1023 done += actual_len;
1024
1025 /* Transactions are done when when either all data is transferred or
1026 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1027 * is executed.
1028 */
1029 } while (((done < len) && !stop_transfer) || complete_split);
1030
1031 writel(0, &hc_regs->hcintmsk);
1032 writel(0xFFFFFFFF, &hc_regs->hcint);
1033
1034 dev->status = 0;
1035 dev->act_len = done;
1036
1037 return ret;
1038 }
1039
1040 /* U-Boot USB transmission interface */
_submit_bulk_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len)1041 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1042 unsigned long pipe, void *buffer, int len)
1043 {
1044 int devnum = usb_pipedevice(pipe);
1045 int ep = usb_pipeendpoint(pipe);
1046 u8* pid;
1047
1048 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1049 dev->status = 0;
1050 return -EINVAL;
1051 }
1052
1053 if (usb_pipein(pipe))
1054 pid = &priv->in_data_toggle[devnum][ep];
1055 else
1056 pid = &priv->out_data_toggle[devnum][ep];
1057
1058 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1059 }
1060
_submit_control_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1061 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1062 unsigned long pipe, void *buffer, int len,
1063 struct devrequest *setup)
1064 {
1065 int devnum = usb_pipedevice(pipe);
1066 int ret, act_len;
1067 u8 pid;
1068 /* For CONTROL endpoint pid should start with DATA1 */
1069 int status_direction;
1070
1071 if (devnum == priv->root_hub_devnum) {
1072 dev->status = 0;
1073 dev->speed = USB_SPEED_HIGH;
1074 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1075 setup);
1076 }
1077
1078 /* SETUP stage */
1079 pid = DWC2_HC_PID_SETUP;
1080 do {
1081 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1082 } while (ret == -EAGAIN);
1083 if (ret)
1084 return ret;
1085
1086 /* DATA stage */
1087 act_len = 0;
1088 if (buffer) {
1089 pid = DWC2_HC_PID_DATA1;
1090 do {
1091 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1092 buffer, len);
1093 act_len += dev->act_len;
1094 buffer += dev->act_len;
1095 len -= dev->act_len;
1096 } while (ret == -EAGAIN);
1097 if (ret)
1098 return ret;
1099 status_direction = usb_pipeout(pipe);
1100 } else {
1101 /* No-data CONTROL always ends with an IN transaction */
1102 status_direction = 1;
1103 }
1104
1105 /* STATUS stage */
1106 pid = DWC2_HC_PID_DATA1;
1107 do {
1108 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1109 priv->status_buffer, 0);
1110 } while (ret == -EAGAIN);
1111 if (ret)
1112 return ret;
1113
1114 dev->act_len = act_len;
1115
1116 return 0;
1117 }
1118
_submit_int_msg(struct dwc2_priv * priv,struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval,bool nonblock)1119 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1120 unsigned long pipe, void *buffer, int len, int interval,
1121 bool nonblock)
1122 {
1123 unsigned long timeout;
1124 int ret;
1125
1126 /* FIXME: what is interval? */
1127
1128 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1129 for (;;) {
1130 if (get_timer(0) > timeout) {
1131 dev_err(dev, "Timeout poll on interrupt endpoint\n");
1132 return -ETIMEDOUT;
1133 }
1134 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1135 if ((ret != -EAGAIN) || nonblock)
1136 return ret;
1137 }
1138 }
1139
dwc2_reset(struct udevice * dev)1140 static int dwc2_reset(struct udevice *dev)
1141 {
1142 int ret;
1143 struct dwc2_priv *priv = dev_get_priv(dev);
1144
1145 ret = reset_get_bulk(dev, &priv->resets);
1146 if (ret) {
1147 dev_warn(dev, "Can't get reset: %d\n", ret);
1148 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1149 * DT property is not present.
1150 */
1151 if (ret == -ENOENT || ret == -ENOTSUPP)
1152 return 0;
1153 else
1154 return ret;
1155 }
1156
1157 /* force reset to clear all IP register */
1158 reset_assert_bulk(&priv->resets);
1159 ret = reset_deassert_bulk(&priv->resets);
1160 if (ret) {
1161 reset_release_bulk(&priv->resets);
1162 dev_err(dev, "Failed to reset: %d\n", ret);
1163 return ret;
1164 }
1165
1166 return 0;
1167 }
1168
dwc2_init_common(struct udevice * dev,struct dwc2_priv * priv)1169 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1170 {
1171 struct dwc2_core_regs *regs = priv->regs;
1172 uint32_t snpsid;
1173 int i, j;
1174 int ret;
1175
1176 ret = dwc2_reset(dev);
1177 if (ret)
1178 return ret;
1179
1180 snpsid = readl(®s->gsnpsid);
1181 dev_info(dev, "Core Release: %x.%03x\n",
1182 snpsid >> 12 & 0xf, snpsid & 0xfff);
1183
1184 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1185 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1186 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1187 snpsid);
1188 return -ENODEV;
1189 }
1190
1191 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1192 priv->ext_vbus = 1;
1193 #else
1194 priv->ext_vbus = 0;
1195 #endif
1196
1197 dwc_otg_core_init(priv);
1198 dwc_otg_core_host_init(dev, regs);
1199
1200 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1201 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1202 DWC2_HPRT0_PRTOVRCURRCHNG,
1203 DWC2_HPRT0_PRTRST);
1204 mdelay(50);
1205 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1206 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1207 DWC2_HPRT0_PRTRST);
1208
1209 for (i = 0; i < MAX_DEVICE; i++) {
1210 for (j = 0; j < MAX_ENDPOINT; j++) {
1211 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1212 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1213 }
1214 }
1215
1216 /*
1217 * Add a 1 second delay here. This gives the host controller
1218 * a bit time before the comminucation with the USB devices
1219 * is started (the bus is scanned) and fixes the USB detection
1220 * problems with some problematic USB keys.
1221 */
1222 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1223 mdelay(1000);
1224
1225 printf("USB DWC2\n");
1226
1227 return 0;
1228 }
1229
dwc2_uninit_common(struct dwc2_core_regs * regs)1230 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1231 {
1232 /* Put everything in reset. */
1233 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1234 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1235 DWC2_HPRT0_PRTOVRCURRCHNG,
1236 DWC2_HPRT0_PRTRST);
1237 }
1238
1239 #if !CONFIG_IS_ENABLED(DM_USB)
submit_control_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,struct devrequest * setup)1240 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1241 int len, struct devrequest *setup)
1242 {
1243 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1244 }
1245
submit_bulk_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len)1246 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1247 int len)
1248 {
1249 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1250 }
1251
submit_int_msg(struct usb_device * dev,unsigned long pipe,void * buffer,int len,int interval,bool nonblock)1252 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1253 int len, int interval, bool nonblock)
1254 {
1255 return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1256 nonblock);
1257 }
1258
1259 /* U-Boot USB control interface */
usb_lowlevel_init(int index,enum usb_init_type init,void ** controller)1260 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1261 {
1262 struct dwc2_priv *priv = &local;
1263
1264 memset(priv, '\0', sizeof(*priv));
1265 priv->root_hub_devnum = 0;
1266 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1267 priv->aligned_buffer = aligned_buffer_addr;
1268 priv->status_buffer = status_buffer_addr;
1269
1270 /* board-dependant init */
1271 if (board_usb_init(index, USB_INIT_HOST))
1272 return -1;
1273
1274 return dwc2_init_common(NULL, priv);
1275 }
1276
usb_lowlevel_stop(int index)1277 int usb_lowlevel_stop(int index)
1278 {
1279 dwc2_uninit_common(local.regs);
1280
1281 return 0;
1282 }
1283 #endif
1284
1285 #if CONFIG_IS_ENABLED(DM_USB)
dwc2_submit_control_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,struct devrequest * setup)1286 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1287 unsigned long pipe, void *buffer, int length,
1288 struct devrequest *setup)
1289 {
1290 struct dwc2_priv *priv = dev_get_priv(dev);
1291
1292 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1293 dev->name, udev, udev->dev->name, udev->portnr);
1294
1295 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1296 }
1297
dwc2_submit_bulk_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length)1298 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1299 unsigned long pipe, void *buffer, int length)
1300 {
1301 struct dwc2_priv *priv = dev_get_priv(dev);
1302
1303 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1304
1305 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1306 }
1307
dwc2_submit_int_msg(struct udevice * dev,struct usb_device * udev,unsigned long pipe,void * buffer,int length,int interval,bool nonblock)1308 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1309 unsigned long pipe, void *buffer, int length,
1310 int interval, bool nonblock)
1311 {
1312 struct dwc2_priv *priv = dev_get_priv(dev);
1313
1314 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1315
1316 return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1317 nonblock);
1318 }
1319
dwc2_usb_ofdata_to_platdata(struct udevice * dev)1320 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1321 {
1322 struct dwc2_priv *priv = dev_get_priv(dev);
1323 fdt_addr_t addr;
1324
1325 addr = dev_read_addr(dev);
1326 if (addr == FDT_ADDR_T_NONE)
1327 return -EINVAL;
1328 priv->regs = (struct dwc2_core_regs *)addr;
1329
1330 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1331 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1332
1333 return 0;
1334 }
1335
dwc2_setup_phy(struct udevice * dev)1336 static int dwc2_setup_phy(struct udevice *dev)
1337 {
1338 struct dwc2_priv *priv = dev_get_priv(dev);
1339 int ret;
1340
1341 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1342 if (ret) {
1343 if (ret == -ENOENT)
1344 return 0; /* no PHY, nothing to do */
1345 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1346 return ret;
1347 }
1348
1349 ret = generic_phy_init(&priv->phy);
1350 if (ret) {
1351 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1352 return ret;
1353 }
1354
1355 ret = generic_phy_power_on(&priv->phy);
1356 if (ret) {
1357 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1358 generic_phy_exit(&priv->phy);
1359 return ret;
1360 }
1361
1362 return 0;
1363 }
1364
dwc2_shutdown_phy(struct udevice * dev)1365 static int dwc2_shutdown_phy(struct udevice *dev)
1366 {
1367 struct dwc2_priv *priv = dev_get_priv(dev);
1368 int ret;
1369
1370 /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1371 if (!generic_phy_valid(&priv->phy))
1372 return 0; /* no PHY, nothing to do */
1373
1374 ret = generic_phy_power_off(&priv->phy);
1375 if (ret) {
1376 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1377 return ret;
1378 }
1379
1380 ret = generic_phy_exit(&priv->phy);
1381 if (ret) {
1382 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1383 return ret;
1384 }
1385
1386 return 0;
1387 }
1388
dwc2_clk_init(struct udevice * dev)1389 static int dwc2_clk_init(struct udevice *dev)
1390 {
1391 struct dwc2_priv *priv = dev_get_priv(dev);
1392 int ret;
1393
1394 ret = clk_get_bulk(dev, &priv->clks);
1395 if (ret == -ENOSYS || ret == -ENOENT)
1396 return 0;
1397 if (ret)
1398 return ret;
1399
1400 ret = clk_enable_bulk(&priv->clks);
1401 if (ret) {
1402 clk_release_bulk(&priv->clks);
1403 return ret;
1404 }
1405
1406 return 0;
1407 }
1408
dwc2_usb_probe(struct udevice * dev)1409 static int dwc2_usb_probe(struct udevice *dev)
1410 {
1411 struct dwc2_priv *priv = dev_get_priv(dev);
1412 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1413 int ret;
1414
1415 bus_priv->desc_before_addr = true;
1416
1417 ret = dwc2_clk_init(dev);
1418 if (ret)
1419 return ret;
1420
1421 ret = dwc2_setup_phy(dev);
1422 if (ret)
1423 return ret;
1424
1425 return dwc2_init_common(dev, priv);
1426 }
1427
dwc2_usb_remove(struct udevice * dev)1428 static int dwc2_usb_remove(struct udevice *dev)
1429 {
1430 struct dwc2_priv *priv = dev_get_priv(dev);
1431 int ret;
1432
1433 ret = dwc_vbus_supply_exit(dev);
1434 if (ret)
1435 return ret;
1436
1437 ret = dwc2_shutdown_phy(dev);
1438 if (ret) {
1439 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1440 return ret;
1441 }
1442
1443 dwc2_uninit_common(priv->regs);
1444
1445 reset_release_bulk(&priv->resets);
1446 clk_disable_bulk(&priv->clks);
1447 clk_release_bulk(&priv->clks);
1448
1449 return 0;
1450 }
1451
1452 struct dm_usb_ops dwc2_usb_ops = {
1453 .control = dwc2_submit_control_msg,
1454 .bulk = dwc2_submit_bulk_msg,
1455 .interrupt = dwc2_submit_int_msg,
1456 };
1457
1458 static const struct udevice_id dwc2_usb_ids[] = {
1459 { .compatible = "brcm,bcm2835-usb" },
1460 { .compatible = "brcm,bcm2708-usb" },
1461 { .compatible = "snps,dwc2" },
1462 { }
1463 };
1464
1465 U_BOOT_DRIVER(usb_dwc2) = {
1466 .name = "dwc2_usb",
1467 .id = UCLASS_USB,
1468 .of_match = dwc2_usb_ids,
1469 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1470 .probe = dwc2_usb_probe,
1471 .remove = dwc2_usb_remove,
1472 .ops = &dwc2_usb_ops,
1473 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1474 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1475 };
1476 #endif
1477