1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <log.h>
9 #include <usb.h>
10 #include <errno.h>
11 #include <linux/compiler.h>
12 #include <linux/delay.h>
13 #include <usb/ehci-ci.h>
14 #include <asm/io.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <dm.h>
18 #include <power/regulator.h>
19
20 #include "ehci.h"
21
22 #define MX5_USBOTHER_REGS_OFFSET 0x800
23
24
25 #define MXC_OTG_OFFSET 0
26 #define MXC_H1_OFFSET 0x200
27 #define MXC_H2_OFFSET 0x400
28 #define MXC_H3_OFFSET 0x600
29
30 #define MXC_USBCTRL_OFFSET 0
31 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
32 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
33 #define MXC_USB_CTRL_1_OFFSET 0x10
34 #define MXC_USBH2CTRL_OFFSET 0x14
35 #define MXC_USBH3CTRL_OFFSET 0x18
36
37 /* USB_CTRL */
38 /* OTG wakeup intr enable */
39 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
40 /* OTG power mask */
41 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
42 /* OTG power pin polarity */
43 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
44 /* Host1 ULPI interrupt enable */
45 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
46 /* HOST1 wakeup intr enable */
47 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
48 /* HOST1 power mask */
49 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
50 /* HOST1 power pin polarity */
51 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
52
53 /* USB_PHY_CTRL_FUNC */
54 /* OTG Polarity of Overcurrent */
55 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
56 /* OTG Disable Overcurrent Event */
57 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
58 /* UH1 Polarity of Overcurrent */
59 #define MXC_H1_OC_POL_BIT (1 << 6)
60 /* UH1 Disable Overcurrent Event */
61 #define MXC_H1_OC_DIS_BIT (1 << 5)
62 /* OTG Power Pin Polarity */
63 #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
64
65 /* USBH2CTRL */
66 #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
67 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
68 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
69 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
70 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
71 #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
72
73 /* USBH3CTRL */
74 #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
75 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
76 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
77 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
78 #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
79
80 /* USB_CTRL_1 */
81 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
82
mxc_set_usbcontrol(int port,unsigned int flags)83 int mxc_set_usbcontrol(int port, unsigned int flags)
84 {
85 unsigned int v;
86 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
87 void __iomem *usbother_base;
88 int ret = 0;
89
90 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
91
92 switch (port) {
93 case 0: /* OTG port */
94 if (flags & MXC_EHCI_INTERNAL_PHY) {
95 v = __raw_readl(usbother_base +
96 MXC_USB_PHY_CTR_FUNC_OFFSET);
97 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
98 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
99 else
100 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
101 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
102 /* OC/USBPWR is used */
103 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
104 else
105 /* OC/USBPWR is not used */
106 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
107 #ifdef CONFIG_MX51
108 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
109 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
110 else
111 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
112 #endif
113 __raw_writel(v, usbother_base +
114 MXC_USB_PHY_CTR_FUNC_OFFSET);
115
116 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
117 #ifdef CONFIG_MX51
118 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
119 v &= ~MXC_OTG_UCTRL_OPM_BIT;
120 else
121 v |= MXC_OTG_UCTRL_OPM_BIT;
122 #endif
123 #ifdef CONFIG_MX53
124 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
125 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
126 else
127 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
128 #endif
129 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
130 }
131 break;
132 case 1: /* Host 1 ULPI */
133 #ifdef CONFIG_MX51
134 /* The clock for the USBH1 ULPI port will come externally
135 from the PHY. */
136 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
137 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
138 MXC_USB_CTRL_1_OFFSET);
139 #endif
140
141 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
142 #ifdef CONFIG_MX51
143 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
144 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
145 else
146 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
147 #endif
148 #ifdef CONFIG_MX53
149 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
150 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
151 else
152 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
153 #endif
154 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
155
156 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
157 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
158 v |= MXC_H1_OC_POL_BIT;
159 else
160 v &= ~MXC_H1_OC_POL_BIT;
161 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
162 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
163 else
164 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
165 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
166
167 break;
168 case 2: /* Host 2 ULPI */
169 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
170 #ifdef CONFIG_MX51
171 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
172 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
173 else
174 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
175 #endif
176 #ifdef CONFIG_MX53
177 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
178 v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
179 else
180 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
181 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
182 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
183 else
184 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
185 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
186 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
187 else
188 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
189 #endif
190 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
191 break;
192 #ifdef CONFIG_MX53
193 case 3: /* Host 3 ULPI */
194 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
195 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
196 v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
197 else
198 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
199 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
200 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
201 else
202 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
203 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
204 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
205 else
206 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
207 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
208 break;
209 #endif
210 }
211
212 return ret;
213 }
214
board_ehci_hcd_init(int port)215 int __weak board_ehci_hcd_init(int port)
216 {
217 return 0;
218 }
219
board_ehci_hcd_postinit(struct usb_ehci * ehci,int port)220 void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
221 {
222 }
223
mx5_ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)224 __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
225 uint32_t *reg)
226 {
227 mdelay(50);
228 }
229
230 #if !CONFIG_IS_ENABLED(DM_USB)
231 static const struct ehci_ops mx5_ehci_ops = {
232 .powerup_fixup = mx5_ehci_powerup_fixup,
233 };
234
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)235 int ehci_hcd_init(int index, enum usb_init_type init,
236 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
237 {
238 struct usb_ehci *ehci;
239
240 /* The only user for this is efikamx-usb */
241 ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
242 set_usboh3_clk();
243 enable_usboh3_clk(true);
244 set_usb_phy_clk();
245 enable_usb_phy1_clk(true);
246 enable_usb_phy2_clk(true);
247 mdelay(1);
248
249 /* Do board specific initialization */
250 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
251
252 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
253 (0x200 * CONFIG_MXC_USB_PORT));
254 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
255 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
256 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
257 setbits_le32(&ehci->usbmode, CM_HOST);
258
259 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
260 setbits_le32(&ehci->portsc, USB_EN);
261
262 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
263 mdelay(10);
264
265 /* Do board specific post-initialization */
266 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
267
268 return 0;
269 }
270
ehci_hcd_stop(int index)271 int ehci_hcd_stop(int index)
272 {
273 return 0;
274 }
275 #else /* CONFIG_IS_ENABLED(DM_USB) */
276 struct ehci_mx5_priv_data {
277 struct ehci_ctrl ctrl;
278 struct usb_ehci *ehci;
279 struct udevice *vbus_supply;
280 enum usb_init_type init_type;
281 int portnr;
282 };
283
284 static const struct ehci_ops mx5_ehci_ops = {
285 .powerup_fixup = mx5_ehci_powerup_fixup,
286 };
287
ehci_usb_ofdata_to_platdata(struct udevice * dev)288 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
289 {
290 struct usb_platdata *plat = dev_get_platdata(dev);
291 const char *mode;
292
293 mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
294 if (mode) {
295 if (strcmp(mode, "peripheral") == 0)
296 plat->init_type = USB_INIT_DEVICE;
297 else if (strcmp(mode, "host") == 0)
298 plat->init_type = USB_INIT_HOST;
299 else
300 return -EINVAL;
301 }
302
303 return 0;
304 }
305
ehci_usb_probe(struct udevice * dev)306 static int ehci_usb_probe(struct udevice *dev)
307 {
308 struct usb_platdata *plat = dev_get_platdata(dev);
309 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
310 struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
311 enum usb_init_type type = plat->init_type;
312 struct ehci_hccr *hccr;
313 struct ehci_hcor *hcor;
314 int ret;
315
316 set_usboh3_clk();
317 enable_usboh3_clk(true);
318 set_usb_phy_clk();
319 enable_usb_phy1_clk(true);
320 enable_usb_phy2_clk(true);
321 mdelay(1);
322
323 priv->ehci = ehci;
324 priv->portnr = dev->seq;
325 priv->init_type = type;
326
327 ret = device_get_supply_regulator(dev, "vbus-supply",
328 &priv->vbus_supply);
329 if (ret)
330 debug("%s: No vbus supply\n", dev->name);
331
332 if (!ret && priv->vbus_supply) {
333 ret = regulator_set_enable(priv->vbus_supply,
334 (type == USB_INIT_DEVICE) ?
335 false : true);
336 if (ret) {
337 puts("Error enabling VBUS supply\n");
338 return ret;
339 }
340 }
341
342 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
343 hcor = (struct ehci_hcor *)((uint32_t)hccr +
344 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
345 setbits_le32(&ehci->usbmode, CM_HOST);
346
347 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
348 setbits_le32(&ehci->portsc, USB_EN);
349
350 mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
351 mdelay(10);
352
353 return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
354 priv->init_type);
355 }
356
357 static const struct udevice_id mx5_usb_ids[] = {
358 { .compatible = "fsl,imx53-usb" },
359 { }
360 };
361
362 U_BOOT_DRIVER(usb_mx5) = {
363 .name = "ehci_mx5",
364 .id = UCLASS_USB,
365 .of_match = mx5_usb_ids,
366 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
367 .probe = ehci_usb_probe,
368 .remove = ehci_deregister,
369 .ops = &ehci_usb_ops,
370 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
371 .priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
372 .flags = DM_FLAG_ALLOC_PRIV_DMA,
373 };
374 #endif /* !CONFIG_IS_ENABLED(DM_USB) */
375