1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * QorIQ RDB boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #if defined(CONFIG_TARGET_P1020MBG) 16 #define CONFIG_BOARDNAME "P1020MBG-PC" 17 #define CONFIG_VSC7385_ENET 18 #define CONFIG_SLIC 19 #define __SW_BOOT_MASK 0x03 20 #define __SW_BOOT_NOR 0xe4 21 #define __SW_BOOT_SD 0x54 22 #define CONFIG_SYS_L2_SIZE (256 << 10) 23 #endif 24 25 #if defined(CONFIG_TARGET_P1020UTM) 26 #define CONFIG_BOARDNAME "P1020UTM-PC" 27 #define __SW_BOOT_MASK 0x03 28 #define __SW_BOOT_NOR 0xe0 29 #define __SW_BOOT_SD 0x50 30 #define CONFIG_SYS_L2_SIZE (256 << 10) 31 #endif 32 33 #if defined(CONFIG_TARGET_P1020RDB_PC) 34 #define CONFIG_BOARDNAME "P1020RDB-PC" 35 #define CONFIG_NAND_FSL_ELBC 36 #define CONFIG_VSC7385_ENET 37 #define CONFIG_SLIC 38 #define __SW_BOOT_MASK 0x03 39 #define __SW_BOOT_NOR 0x5c 40 #define __SW_BOOT_SPI 0x1c 41 #define __SW_BOOT_SD 0x9c 42 #define __SW_BOOT_NAND 0xec 43 #define __SW_BOOT_PCIE 0x6c 44 #define CONFIG_SYS_L2_SIZE (256 << 10) 45 #endif 46 47 /* 48 * P1020RDB-PD board has user selectable switches for evaluating different 49 * frequency and boot options for the P1020 device. The table that 50 * follow describe the available options. The front six binary number was in 51 * accordance with SW3[1:6]. 52 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off 53 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off 54 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off 55 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off 56 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off 57 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off 58 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off 59 */ 60 #if defined(CONFIG_TARGET_P1020RDB_PD) 61 #define CONFIG_BOARDNAME "P1020RDB-PD" 62 #define CONFIG_NAND_FSL_ELBC 63 #define CONFIG_VSC7385_ENET 64 #define CONFIG_SLIC 65 #define __SW_BOOT_MASK 0x03 66 #define __SW_BOOT_NOR 0x64 67 #define __SW_BOOT_SPI 0x34 68 #define __SW_BOOT_SD 0x24 69 #define __SW_BOOT_NAND 0x44 70 #define __SW_BOOT_PCIE 0x74 71 #define CONFIG_SYS_L2_SIZE (256 << 10) 72 /* 73 * Dynamic MTD Partition support with mtdparts 74 */ 75 #endif 76 77 #if defined(CONFIG_TARGET_P1021RDB) 78 #define CONFIG_BOARDNAME "P1021RDB-PC" 79 #define CONFIG_NAND_FSL_ELBC 80 #define CONFIG_VSC7385_ENET 81 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 82 addresses in the LBC */ 83 #define __SW_BOOT_MASK 0x03 84 #define __SW_BOOT_NOR 0x5c 85 #define __SW_BOOT_SPI 0x1c 86 #define __SW_BOOT_SD 0x9c 87 #define __SW_BOOT_NAND 0xec 88 #define __SW_BOOT_PCIE 0x6c 89 #define CONFIG_SYS_L2_SIZE (256 << 10) 90 /* 91 * Dynamic MTD Partition support with mtdparts 92 */ 93 #endif 94 95 #if defined(CONFIG_TARGET_P1024RDB) 96 #define CONFIG_BOARDNAME "P1024RDB" 97 #define CONFIG_NAND_FSL_ELBC 98 #define CONFIG_SLIC 99 #define __SW_BOOT_MASK 0xf3 100 #define __SW_BOOT_NOR 0x00 101 #define __SW_BOOT_SPI 0x08 102 #define __SW_BOOT_SD 0x04 103 #define __SW_BOOT_NAND 0x0c 104 #define CONFIG_SYS_L2_SIZE (256 << 10) 105 #endif 106 107 #if defined(CONFIG_TARGET_P1025RDB) 108 #define CONFIG_BOARDNAME "P1025RDB" 109 #define CONFIG_NAND_FSL_ELBC 110 #define CONFIG_SLIC 111 112 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of 113 addresses in the LBC */ 114 #define __SW_BOOT_MASK 0xf3 115 #define __SW_BOOT_NOR 0x00 116 #define __SW_BOOT_SPI 0x08 117 #define __SW_BOOT_SD 0x04 118 #define __SW_BOOT_NAND 0x0c 119 #define CONFIG_SYS_L2_SIZE (256 << 10) 120 #endif 121 122 #if defined(CONFIG_TARGET_P2020RDB) 123 #define CONFIG_BOARDNAME "P2020RDB-PC" 124 #define CONFIG_NAND_FSL_ELBC 125 #define CONFIG_VSC7385_ENET 126 #define __SW_BOOT_MASK 0x03 127 #define __SW_BOOT_NOR 0xc8 128 #define __SW_BOOT_SPI 0x28 129 #define __SW_BOOT_SD 0x68 /* or 0x18 */ 130 #define __SW_BOOT_NAND 0xe8 131 #define __SW_BOOT_PCIE 0xa8 132 #define CONFIG_SYS_L2_SIZE (512 << 10) 133 /* 134 * Dynamic MTD Partition support with mtdparts 135 */ 136 #endif 137 138 #ifdef CONFIG_SDCARD 139 #define CONFIG_SPL_FLUSH_IMAGE 140 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 141 #define CONFIG_SPL_PAD_TO 0x20000 142 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 143 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 144 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 145 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 146 #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) 147 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 148 #ifdef CONFIG_SPL_BUILD 149 #define CONFIG_SPL_COMMON_INIT_DDR 150 #endif 151 #endif 152 153 #ifdef CONFIG_SPIFLASH 154 #define CONFIG_SPL_SPI_FLASH_MINIMAL 155 #define CONFIG_SPL_FLUSH_IMAGE 156 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 157 #define CONFIG_SPL_PAD_TO 0x20000 158 #define CONFIG_SPL_MAX_SIZE (128 * 1024) 159 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 160 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 161 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 162 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) 163 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 164 #ifdef CONFIG_SPL_BUILD 165 #define CONFIG_SPL_COMMON_INIT_DDR 166 #endif 167 #endif 168 169 #ifdef CONFIG_MTD_RAW_NAND 170 #ifdef CONFIG_TPL_BUILD 171 #define CONFIG_SPL_FLUSH_IMAGE 172 #define CONFIG_SPL_NAND_INIT 173 #define CONFIG_SPL_COMMON_INIT_DDR 174 #define CONFIG_SPL_MAX_SIZE (128 << 10) 175 #define CONFIG_TPL_TEXT_BASE 0xf8f81000 176 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 177 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 178 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 179 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 180 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 181 #elif defined(CONFIG_SPL_BUILD) 182 #define CONFIG_SPL_INIT_MINIMAL 183 #define CONFIG_SPL_FLUSH_IMAGE 184 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 185 #define CONFIG_SPL_MAX_SIZE 4096 186 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 187 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 188 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 189 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 190 #endif /* not CONFIG_TPL_BUILD */ 191 192 #define CONFIG_SPL_PAD_TO 0x20000 193 #define CONFIG_TPL_PAD_TO 0x20000 194 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 195 #endif 196 197 #ifndef CONFIG_RESET_VECTOR_ADDRESS 198 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 199 #endif 200 201 #ifndef CONFIG_SYS_MONITOR_BASE 202 #ifdef CONFIG_TPL_BUILD 203 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE 204 #elif defined(CONFIG_SPL_BUILD) 205 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 206 #else 207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 208 #endif 209 #endif 210 211 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 212 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 213 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 214 215 #define CONFIG_ENV_OVERWRITE 216 217 #define CONFIG_SYS_SATA_MAX_DEVICE 2 218 #define CONFIG_LBA48 219 220 #if defined(CONFIG_TARGET_P2020RDB) 221 #define CONFIG_SYS_CLK_FREQ 100000000 222 #else 223 #define CONFIG_SYS_CLK_FREQ 66666666 224 #endif 225 #define CONFIG_DDR_CLK_FREQ 66666666 226 227 #define CONFIG_HWCONFIG 228 /* 229 * These can be toggled for performance analysis, otherwise use default. 230 */ 231 #define CONFIG_L2_CACHE 232 #define CONFIG_BTB 233 234 #define CONFIG_ENABLE_36BIT_PHYS 235 236 #ifdef CONFIG_PHYS_64BIT 237 #define CONFIG_ADDR_MAP 1 238 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 239 #endif 240 241 #define CONFIG_SYS_CCSRBAR 0xffe00000 242 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 243 244 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k 245 SPL code*/ 246 #ifdef CONFIG_SPL_BUILD 247 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 248 #endif 249 250 /* DDR Setup */ 251 #define CONFIG_SYS_DDR_RAW_TIMING 252 #define CONFIG_DDR_SPD 253 #define CONFIG_SYS_SPD_BUS_NUM 1 254 #define SPD_EEPROM_ADDRESS 0x52 255 256 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 257 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G 258 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 259 #else 260 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G 261 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 262 #endif 263 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 264 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 265 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 266 267 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 268 269 /* Default settings for DDR3 */ 270 #ifndef CONFIG_TARGET_P2020RDB 271 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 272 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 273 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 274 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f 275 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 276 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 277 278 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 279 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 280 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 281 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 282 283 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 284 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 285 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 286 #define CONFIG_SYS_DDR_RCW_1 0x00000000 287 #define CONFIG_SYS_DDR_RCW_2 0x00000000 288 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ 289 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 290 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 291 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 292 293 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 294 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 295 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 296 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF 297 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 298 #define CONFIG_SYS_DDR_MODE_1 0x40461520 299 #define CONFIG_SYS_DDR_MODE_2 0x8000c000 300 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000 301 #endif 302 303 #undef CONFIG_CLOCKS_IN_MHZ 304 305 /* 306 * Memory map 307 * 308 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable 309 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 310 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 311 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable 312 * (early boot only) 313 * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 314 * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 315 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 316 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 317 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 318 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable 319 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 320 */ 321 322 /* 323 * Local Bus Definitions 324 */ 325 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) 326 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 327 #define CONFIG_SYS_FLASH_BASE 0xec000000 328 #elif defined(CONFIG_TARGET_P1020UTM) 329 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 330 #define CONFIG_SYS_FLASH_BASE 0xee000000 331 #else 332 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ 333 #define CONFIG_SYS_FLASH_BASE 0xef000000 334 #endif 335 336 #ifdef CONFIG_PHYS_64BIT 337 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 338 #else 339 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 340 #endif 341 342 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 343 | BR_PS_16 | BR_V) 344 345 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 346 347 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 348 #define CONFIG_SYS_FLASH_QUIET_TEST 349 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 350 351 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 352 353 #undef CONFIG_SYS_FLASH_CHECKSUM 354 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 355 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 356 357 #define CONFIG_SYS_FLASH_EMPTY_INFO 358 359 /* Nand Flash */ 360 #ifdef CONFIG_NAND_FSL_ELBC 361 #define CONFIG_SYS_NAND_BASE 0xff800000 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 364 #else 365 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 366 #endif 367 368 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 369 #define CONFIG_SYS_MAX_NAND_DEVICE 1 370 #if defined(CONFIG_TARGET_P1020RDB_PD) 371 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 372 #else 373 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 374 #endif 375 376 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 377 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 378 | BR_PS_8 /* Port Size = 8 bit */ \ 379 | BR_MS_FCM /* MSEL = FCM */ \ 380 | BR_V) /* valid */ 381 #if defined(CONFIG_TARGET_P1020RDB_PD) 382 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 383 | OR_FCM_PGS /* Large Page*/ \ 384 | OR_FCM_CSCT \ 385 | OR_FCM_CST \ 386 | OR_FCM_CHT \ 387 | OR_FCM_SCY_1 \ 388 | OR_FCM_TRLX \ 389 | OR_FCM_EHTR) 390 #else 391 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \ 392 | OR_FCM_CSCT \ 393 | OR_FCM_CST \ 394 | OR_FCM_CHT \ 395 | OR_FCM_SCY_1 \ 396 | OR_FCM_TRLX \ 397 | OR_FCM_EHTR) 398 #endif 399 #endif /* CONFIG_NAND_FSL_ELBC */ 400 401 #define CONFIG_SYS_INIT_RAM_LOCK 402 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 403 #ifdef CONFIG_PHYS_64BIT 404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 406 /* The assembler doesn't like typecast */ 407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 408 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 409 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 410 #else 411 /* Initial L1 address */ 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 415 #endif 416 /* Size of used area in RAM */ 417 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 418 419 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 420 GENERATED_GBL_DATA_SIZE) 421 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 422 423 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 424 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 425 426 #define CONFIG_SYS_CPLD_BASE 0xffa00000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull 429 #else 430 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 431 #endif 432 /* CPLD config size: 1Mb */ 433 #define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \ 434 BR_PS_8 | BR_V) 435 #define CONFIG_CPLD_OR_PRELIM (0xfff009f7) 436 437 #define CONFIG_SYS_PMC_BASE 0xff980000 438 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE 439 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ 440 BR_PS_8 | BR_V) 441 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 442 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ 443 OR_GPCM_EAD) 444 445 #ifdef CONFIG_MTD_RAW_NAND 446 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 447 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 448 #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 449 #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 450 #else 451 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 452 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 453 #ifdef CONFIG_NAND_FSL_ELBC 454 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ 455 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 456 #endif 457 #endif 458 #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ 459 #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ 460 461 /* Vsc7385 switch */ 462 #ifdef CONFIG_VSC7385_ENET 463 #define CONFIG_SYS_VSC7385_BASE 0xffb00000 464 465 #ifdef CONFIG_PHYS_64BIT 466 #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull 467 #else 468 #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE 469 #endif 470 471 #define CONFIG_SYS_VSC7385_BR_PRELIM \ 472 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) 473 #define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ 474 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ 475 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 476 477 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM 478 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM 479 480 /* The size of the VSC7385 firmware image */ 481 #define CONFIG_VSC7385_IMAGE_SIZE 8192 482 #endif 483 484 /* 485 * Config the L2 Cache as L2 SRAM 486 */ 487 #if defined(CONFIG_SPL_BUILD) 488 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 489 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 490 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 491 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 492 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 493 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 494 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) 495 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) 496 #if defined(CONFIG_TARGET_P2020RDB) 497 #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) 498 #else 499 #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) 500 #endif 501 #elif defined(CONFIG_MTD_RAW_NAND) 502 #ifdef CONFIG_TPL_BUILD 503 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 504 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 505 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 506 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 507 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 508 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 509 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 510 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 511 #else 512 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 513 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 514 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 515 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) 516 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 517 #endif /* CONFIG_TPL_BUILD */ 518 #endif 519 #endif 520 521 /* Serial Port - controlled on board with jumper J8 522 * open - index 2 523 * shorted - index 1 524 */ 525 #undef CONFIG_SERIAL_SOFTWARE_FIFO 526 #define CONFIG_SYS_NS16550_SERIAL 527 #define CONFIG_SYS_NS16550_REG_SIZE 1 528 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 529 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 530 #define CONFIG_NS16550_MIN_FUNCTIONS 531 #endif 532 533 #define CONFIG_SYS_BAUDRATE_TABLE \ 534 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 535 536 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 537 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 538 539 /* I2C */ 540 #ifndef CONFIG_DM_I2C 541 #define CONFIG_SYS_I2C 542 #define CONFIG_SYS_FSL_I2C_SPEED 400000 543 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 544 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 545 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 546 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 547 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 548 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 549 #else 550 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 551 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 552 #endif 553 554 #define CONFIG_SYS_I2C_FSL 555 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 556 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ 557 558 /* 559 * I2C2 EEPROM 560 */ 561 #undef CONFIG_ID_EEPROM 562 563 #define CONFIG_RTC_PT7C4338 564 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 565 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 566 567 /* enable read and write access to EEPROM */ 568 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 569 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 570 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 571 572 #if defined(CONFIG_PCI) 573 /* 574 * General PCI 575 * Memory space is mapped 1-1, but I/O space must start from 0. 576 */ 577 578 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 579 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 580 #ifdef CONFIG_PHYS_64BIT 581 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 582 #else 583 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 584 #endif 585 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 586 #ifdef CONFIG_PHYS_64BIT 587 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 588 #else 589 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 590 #endif 591 592 /* controller 1, Slot 2, tgtid 1, Base address a000 */ 593 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 596 #else 597 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 598 #endif 599 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 600 #ifdef CONFIG_PHYS_64BIT 601 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 602 #else 603 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 604 #endif 605 606 #if !defined(CONFIG_DM_PCI) 607 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 608 #define CONFIG_PCI_INDIRECT_BRIDGE 609 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" 610 #ifdef CONFIG_PHYS_64BIT 611 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 612 #else 613 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 614 #endif 615 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 616 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 617 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 618 619 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 620 #ifdef CONFIG_PHYS_64BIT 621 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 622 #else 623 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 624 #endif 625 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 626 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 627 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 628 #endif 629 630 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 631 #endif /* CONFIG_PCI */ 632 633 #if defined(CONFIG_TSEC_ENET) 634 #define CONFIG_TSEC1 635 #define CONFIG_TSEC1_NAME "eTSEC1" 636 #define CONFIG_TSEC2 637 #define CONFIG_TSEC2_NAME "eTSEC2" 638 #define CONFIG_TSEC3 639 #define CONFIG_TSEC3_NAME "eTSEC3" 640 641 #define TSEC1_PHY_ADDR 2 642 #define TSEC2_PHY_ADDR 0 643 #define TSEC3_PHY_ADDR 1 644 645 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 646 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 647 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 648 649 #define TSEC1_PHYIDX 0 650 #define TSEC2_PHYIDX 0 651 #define TSEC3_PHYIDX 0 652 653 #define CONFIG_ETHPRIME "eTSEC1" 654 655 #define CONFIG_HAS_ETH0 656 #define CONFIG_HAS_ETH1 657 #define CONFIG_HAS_ETH2 658 #endif /* CONFIG_TSEC_ENET */ 659 660 #ifdef CONFIG_QE 661 /* QE microcode/firmware address */ 662 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 663 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 664 #endif /* CONFIG_QE */ 665 666 #ifdef CONFIG_TARGET_P1025RDB 667 /* 668 * QE UEC ethernet configuration 669 */ 670 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 671 672 #undef CONFIG_UEC_ETH 673 #define CONFIG_PHY_MODE_NEED_CHANGE 674 675 #define CONFIG_UEC_ETH1 /* ETH1 */ 676 #define CONFIG_HAS_ETH0 677 678 #ifdef CONFIG_UEC_ETH1 679 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 680 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 681 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 682 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 683 #define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ 684 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 685 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 686 #endif /* CONFIG_UEC_ETH1 */ 687 688 #define CONFIG_UEC_ETH5 /* ETH5 */ 689 #define CONFIG_HAS_ETH1 690 691 #ifdef CONFIG_UEC_ETH5 692 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 693 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 694 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 695 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 696 #define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ 697 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 698 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 699 #endif /* CONFIG_UEC_ETH5 */ 700 #endif /* CONFIG_TARGET_P1025RDB */ 701 702 /* 703 * Environment 704 */ 705 #if defined(CONFIG_SDCARD) 706 #define CONFIG_FSL_FIXED_MMC_LOCATION 707 #define CONFIG_SYS_MMC_ENV_DEV 0 708 #elif defined(CONFIG_MTD_RAW_NAND) 709 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 710 #ifdef CONFIG_TPL_BUILD 711 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 712 #endif 713 #elif defined(CONFIG_SYS_RAMBOOT) 714 #define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 715 #endif 716 717 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 718 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 719 720 /* 721 * USB 722 */ 723 #define CONFIG_HAS_FSL_DR_USB 724 725 #if defined(CONFIG_HAS_FSL_DR_USB) 726 #ifdef CONFIG_USB_EHCI_HCD 727 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 728 #define CONFIG_USB_EHCI_FSL 729 #endif 730 #endif 731 732 #if defined(CONFIG_TARGET_P1020RDB_PD) 733 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 734 #endif 735 736 #ifdef CONFIG_MMC 737 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 738 #endif 739 740 #undef CONFIG_WATCHDOG /* watchdog disabled */ 741 742 /* 743 * Miscellaneous configurable options 744 */ 745 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 746 747 /* 748 * For booting Linux, the board info and command line data 749 * have to be in the first 64 MB of memory, since this is 750 * the maximum mapped by the Linux kernel during initialization. 751 */ 752 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 753 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 754 755 #if defined(CONFIG_CMD_KGDB) 756 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 757 #endif 758 759 /* 760 * Environment Configuration 761 */ 762 #define CONFIG_HOSTNAME "unknown" 763 #define CONFIG_ROOTPATH "/opt/nfsroot" 764 #define CONFIG_BOOTFILE "uImage" 765 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 766 767 /* default location for tftp and bootm */ 768 #define CONFIG_LOADADDR 1000000 769 770 #ifdef __SW_BOOT_NOR 771 #define __NOR_RST_CMD \ 772 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ 773 i2c mw 18 3 __SW_BOOT_MASK 1; reset 774 #endif 775 #ifdef __SW_BOOT_SPI 776 #define __SPI_RST_CMD \ 777 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ 778 i2c mw 18 3 __SW_BOOT_MASK 1; reset 779 #endif 780 #ifdef __SW_BOOT_SD 781 #define __SD_RST_CMD \ 782 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ 783 i2c mw 18 3 __SW_BOOT_MASK 1; reset 784 #endif 785 #ifdef __SW_BOOT_NAND 786 #define __NAND_RST_CMD \ 787 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ 788 i2c mw 18 3 __SW_BOOT_MASK 1; reset 789 #endif 790 #ifdef __SW_BOOT_PCIE 791 #define __PCIE_RST_CMD \ 792 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ 793 i2c mw 18 3 __SW_BOOT_MASK 1; reset 794 #endif 795 796 #define CONFIG_EXTRA_ENV_SETTINGS \ 797 "netdev=eth0\0" \ 798 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 799 "loadaddr=1000000\0" \ 800 "bootfile=uImage\0" \ 801 "tftpflash=tftpboot $loadaddr $uboot; " \ 802 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 803 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 804 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 805 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 806 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 807 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ 808 "consoledev=ttyS0\0" \ 809 "ramdiskaddr=2000000\0" \ 810 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 811 "fdtaddr=1e00000\0" \ 812 "bdev=sda1\0" \ 813 "jffs2nor=mtdblock3\0" \ 814 "norbootaddr=ef080000\0" \ 815 "norfdtaddr=ef040000\0" \ 816 "jffs2nand=mtdblock9\0" \ 817 "nandbootaddr=100000\0" \ 818 "nandfdtaddr=80000\0" \ 819 "ramdisk_size=120000\0" \ 820 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ 821 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ 822 __stringify(__NOR_RST_CMD)"\0" \ 823 __stringify(__SPI_RST_CMD)"\0" \ 824 __stringify(__SD_RST_CMD)"\0" \ 825 __stringify(__NAND_RST_CMD)"\0" \ 826 __stringify(__PCIE_RST_CMD)"\0" 827 828 #define CONFIG_NFSBOOTCOMMAND \ 829 "setenv bootargs root=/dev/nfs rw " \ 830 "nfsroot=$serverip:$rootpath " \ 831 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "tftp $loadaddr $bootfile;" \ 834 "tftp $fdtaddr $fdtfile;" \ 835 "bootm $loadaddr - $fdtaddr" 836 837 #define CONFIG_HDBOOT \ 838 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 839 "console=$consoledev,$baudrate $othbootargs;" \ 840 "usb start;" \ 841 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 842 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 843 "bootm $loadaddr - $fdtaddr" 844 845 #define CONFIG_USB_FAT_BOOT \ 846 "setenv bootargs root=/dev/ram rw " \ 847 "console=$consoledev,$baudrate $othbootargs " \ 848 "ramdisk_size=$ramdisk_size;" \ 849 "usb start;" \ 850 "fatload usb 0:2 $loadaddr $bootfile;" \ 851 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 852 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 853 "bootm $loadaddr $ramdiskaddr $fdtaddr" 854 855 #define CONFIG_USB_EXT2_BOOT \ 856 "setenv bootargs root=/dev/ram rw " \ 857 "console=$consoledev,$baudrate $othbootargs " \ 858 "ramdisk_size=$ramdisk_size;" \ 859 "usb start;" \ 860 "ext2load usb 0:4 $loadaddr $bootfile;" \ 861 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 862 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 863 "bootm $loadaddr $ramdiskaddr $fdtaddr" 864 865 #define CONFIG_NORBOOT \ 866 "setenv bootargs root=/dev/$jffs2nor rw " \ 867 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 868 "bootm $norbootaddr - $norfdtaddr" 869 870 #define CONFIG_RAMBOOTCOMMAND \ 871 "setenv bootargs root=/dev/ram rw " \ 872 "console=$consoledev,$baudrate $othbootargs " \ 873 "ramdisk_size=$ramdisk_size;" \ 874 "tftp $ramdiskaddr $ramdiskfile;" \ 875 "tftp $loadaddr $bootfile;" \ 876 "tftp $fdtaddr $fdtfile;" \ 877 "bootm $loadaddr $ramdiskaddr $fdtaddr" 878 879 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 880 881 #endif /* __CONFIG_H */ 882