1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* Tegra clock control functions */ 8 9 #ifndef _TEGRA_CLOCK_H_ 10 #define _TEGRA_CLOCK_H_ 11 12 /* Set of oscillator frequencies supported in the internal API. */ 13 enum clock_osc_freq { 14 /* All in MHz, so 13_0 is 13.0MHz */ 15 CLOCK_OSC_FREQ_13_0, 16 CLOCK_OSC_FREQ_19_2, 17 CLOCK_OSC_FREQ_12_0, 18 CLOCK_OSC_FREQ_26_0, 19 20 CLOCK_OSC_FREQ_COUNT, 21 }; 22 23 /* 24 * Note that no Tegra clock register actually uses all of bits 31:28 as 25 * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in 26 * those cases, nothing is stored in the bits about the mux field, so it's 27 * safe to pretend that the mux field extends all the way to the end of the 28 * register. As such, the U-Boot clock driver is currently a bit lazy, and 29 * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps 30 * them all together and pretends they're all 31:28. 31 */ 32 enum { 33 MASK_BITS_31_30, 34 MASK_BITS_31_29, 35 MASK_BITS_31_28, 36 }; 37 38 #include <asm/arch/clock-tables.h> 39 /* PLL stabilization delay in usec */ 40 #define CLOCK_PLL_STABLE_DELAY_US 300 41 42 /* return the current oscillator clock frequency */ 43 enum clock_osc_freq clock_get_osc_freq(void); 44 45 /** 46 * Start PLL using the provided configuration parameters. 47 * 48 * @param id clock id 49 * @param divm input divider 50 * @param divn feedback divider 51 * @param divp post divider 2^n 52 * @param cpcon charge pump setup control 53 * @param lfcon loop filter setup control 54 * 55 * @returns monotonic time in us that the PLL will be stable 56 */ 57 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 58 u32 divp, u32 cpcon, u32 lfcon); 59 60 /** 61 * Set PLL output frequency 62 * 63 * @param clkid clock id 64 * @param pllout pll output id 65 * @param rate desired output rate 66 * 67 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 68 */ 69 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 70 unsigned rate); 71 72 /** 73 * Read low-level parameters of a PLL. 74 * 75 * @param id clock id to read (note: USB is not supported) 76 * @param divm returns input divider 77 * @param divn returns feedback divider 78 * @param divp returns post divider 2^n 79 * @param cpcon returns charge pump setup control 80 * @param lfcon returns loop filter setup control 81 * 82 * @returns 0 if ok, -1 on error (invalid clock id) 83 */ 84 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 85 u32 *divp, u32 *cpcon, u32 *lfcon); 86 87 /* 88 * Enable a clock 89 * 90 * @param id clock id 91 */ 92 void clock_enable(enum periph_id clkid); 93 94 /* 95 * Disable a clock 96 * 97 * @param id clock id 98 */ 99 void clock_disable(enum periph_id clkid); 100 101 /* 102 * Set whether a clock is enabled or disabled. 103 * 104 * @param id clock id 105 * @param enable 1 to enable, 0 to disable 106 */ 107 void clock_set_enable(enum periph_id clkid, int enable); 108 109 /** 110 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 111 * it out of reset and waits for th delay again. 112 * 113 * @param periph_id peripheral to reset 114 * @param us_delay time to delay in microseconds 115 */ 116 void reset_periph(enum periph_id periph_id, int us_delay); 117 118 /** 119 * Put a peripheral into or out of reset. 120 * 121 * @param periph_id peripheral to reset 122 * @param enable 1 to put into reset, 0 to take out of reset 123 */ 124 void reset_set_enable(enum periph_id periph_id, int enable); 125 126 127 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 128 enum crc_reset_id { 129 /* Things we can hold in reset for each CPU */ 130 crc_rst_cpu = 1, 131 crc_rst_de = 1 << 4, /* What is de? */ 132 crc_rst_watchdog = 1 << 8, 133 crc_rst_debug = 1 << 12, 134 }; 135 136 /** 137 * Put parts of the CPU complex into or out of reset.\ 138 * 139 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 140 * @param which which parts of the complex to affect (OR of crc_reset_id) 141 * @param reset 1 to assert reset, 0 to de-assert 142 */ 143 void reset_cmplx_set_enable(int cpu, int which, int reset); 144 145 /** 146 * Set the source for a peripheral clock. This plus the divisor sets the 147 * clock rate. You need to look up the datasheet to see the meaning of the 148 * source parameter as it changes for each peripheral. 149 * 150 * Warning: This function is only for use pre-relocation. Please use 151 * clock_start_periph_pll() instead. 152 * 153 * @param periph_id peripheral to adjust 154 * @param source source clock (0, 1, 2 or 3) 155 */ 156 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 157 158 /** 159 * This function is similar to clock_ll_set_source() except that it can be 160 * used for clocks with more than 2 mux bits. 161 * 162 * @param periph_id peripheral to adjust 163 * @param mux_bits number of mux bits for the clock 164 * @param source source clock (0-15 depending on mux_bits) 165 */ 166 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 167 unsigned source); 168 169 /** 170 * Set the source and divisor for a peripheral clock. This sets the 171 * clock rate. You need to look up the datasheet to see the meaning of the 172 * source parameter as it changes for each peripheral. 173 * 174 * Warning: This function is only for use pre-relocation. Please use 175 * clock_start_periph_pll() instead. 176 * 177 * @param periph_id peripheral to adjust 178 * @param source source clock (0, 1, 2 or 3) 179 * @param divisor divisor value to use 180 */ 181 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 182 unsigned divisor); 183 184 /** 185 * Start a peripheral PLL clock at the given rate. This also resets the 186 * peripheral. 187 * 188 * @param periph_id peripheral to start 189 * @param parent PLL id of required parent clock 190 * @param rate Required clock rate in Hz 191 * @return rate selected in Hz, or -1U if something went wrong 192 */ 193 unsigned clock_start_periph_pll(enum periph_id periph_id, 194 enum clock_id parent, unsigned rate); 195 196 /** 197 * Returns the rate of a peripheral clock in Hz. Since the caller almost 198 * certainly knows the parent clock (having just set it) we require that 199 * this be passed in so we don't need to work it out. 200 * 201 * @param periph_id peripheral to start 202 * @param parent PLL id of parent clock (used to calculate rate, you 203 * must know this!) 204 * @return clock rate of peripheral in Hz 205 */ 206 unsigned long clock_get_periph_rate(enum periph_id periph_id, 207 enum clock_id parent); 208 209 /** 210 * Adjust peripheral PLL clock to the given rate. This does not reset the 211 * peripheral. If a second stage divisor is not available, pass NULL for 212 * extra_div. If it is available, then this parameter will return the 213 * divisor selected (which will be a power of 2 from 1 to 256). 214 * 215 * @param periph_id peripheral to start 216 * @param parent PLL id of required parent clock 217 * @param rate Required clock rate in Hz 218 * @param extra_div value for the second-stage divisor (NULL if one is 219 not available) 220 * @return rate selected in Hz, or -1U if something went wrong 221 */ 222 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 223 enum clock_id parent, unsigned rate, int *extra_div); 224 225 /** 226 * Returns the clock rate of a specified clock, in Hz. 227 * 228 * @param parent PLL id of clock to check 229 * @return rate of clock in Hz 230 */ 231 unsigned clock_get_rate(enum clock_id clkid); 232 233 /** 234 * Start up a UART using low-level calls 235 * 236 * Prior to relocation clock_start_periph_pll() cannot be called. This 237 * function provides a way to set up a UART using low-level calls which 238 * do not require BSS. 239 * 240 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 241 */ 242 void clock_ll_start_uart(enum periph_id periph_id); 243 244 /** 245 * Decode a peripheral ID from a device tree node. 246 * 247 * This works by looking up the peripheral's 'clocks' node and reading out 248 * the second cell, which is the clock number / peripheral ID. 249 * 250 * @param blob FDT blob to use 251 * @param node Node to look at 252 * @return peripheral ID, or PERIPH_ID_NONE if none 253 */ 254 enum periph_id clock_decode_periph_id(const void *blob, int node); 255 256 /** 257 * Checks if the oscillator bypass is enabled (XOBP bit) 258 * 259 * @return 1 if bypass is enabled, 0 if not 260 */ 261 int clock_get_osc_bypass(void); 262 263 /* 264 * Checks that clocks are valid and prints a warning if not 265 * 266 * @return 0 if ok, -1 on error 267 */ 268 int clock_verify(void); 269 270 /* Initialize the clocks */ 271 void clock_init(void); 272 273 /* Initialize the PLLs */ 274 void clock_early_init(void); 275 276 /* Returns a pointer to the clock source register for a peripheral */ 277 u32 *get_periph_source_reg(enum periph_id periph_id); 278 279 /* Returns a pointer to the given 'simple' PLL */ 280 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); 281 282 /** 283 * Given a peripheral ID and the required source clock, this returns which 284 * value should be programmed into the source mux for that peripheral. 285 * 286 * There is special code here to handle the one source type with 5 sources. 287 * 288 * @param periph_id peripheral to start 289 * @param source PLL id of required parent clock 290 * @param mux_bits Set to number of bits in mux register: 2 or 4 291 * @param divider_bits Set to number of divider bits (8 or 16) 292 * @return mux value (0-4, or -1 if not found) 293 */ 294 int get_periph_clock_source(enum periph_id periph_id, 295 enum clock_id parent, int *mux_bits, int *divider_bits); 296 297 /* 298 * Convert a device tree clock ID to our peripheral ID. They are mostly 299 * the same but we are very cautious so we check that a valid clock ID is 300 * provided. 301 * 302 * @param clk_id Clock ID according to tegra30 device tree binding 303 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 304 */ 305 enum periph_id clk_id_to_periph_id(int clk_id); 306 307 /** 308 * Set the output frequency you want for each PLL clock. 309 * PLL output frequencies are programmed by setting their N, M and P values. 310 * The governing equations are: 311 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 312 * where Fo is the output frequency from the PLL. 313 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 314 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 315 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 316 * 317 * @param n PLL feedback divider(DIVN) 318 * @param m PLL input divider(DIVN) 319 * @param p post divider(DIVP) 320 * @param cpcon base PLL charge pump(CPCON) 321 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 322 * be overriden), 1 if PLL is already correct 323 */ 324 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 325 326 /* return 1 if a peripheral ID is in range */ 327 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 328 (id) < CLOCK_TYPE_COUNT) 329 330 /* return 1 if a periphc_internal_id is in range */ 331 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 332 (id) < PERIPHC_COUNT) 333 334 /* SoC-specific TSC init */ 335 void arch_timer_init(void); 336 337 void tegra30_set_up_pllp(void); 338 339 /** 340 * Enable output clock for external peripherals 341 * 342 * @param clk_id Clock ID to output (1, 2 or 3) 343 * @return 0 if OK. -ve on error 344 */ 345 int clock_external_output(int clk_id); 346 347 #endif /* _TEGRA_CLOCK_H_ */ 348