1 /*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <asm/processor.h>
11 #include <asm/io.h>
12 #include <asm/ppc4xx-gpio.h>
13 #include <dtt.h>
14
15 #include "405ep.h"
16 #include <gdsys_fpga.h>
17
18 #include "../common/osd.h"
19
20 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
21 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
22 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
23 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
24
25 #define LATCH2_MC2_PRESENT_N 0x0080
26
27 enum {
28 UNITTYPE_VIDEO_USER = 0,
29 UNITTYPE_MAIN_USER = 1,
30 UNITTYPE_VIDEO_SERVER = 2,
31 UNITTYPE_MAIN_SERVER = 3,
32 };
33
34 enum {
35 HWVER_101 = 0,
36 HWVER_110 = 1,
37 HWVER_120 = 2,
38 HWVER_130 = 3,
39 };
40
41 enum {
42 AUDIO_NONE = 0,
43 AUDIO_TX = 1,
44 AUDIO_RX = 2,
45 AUDIO_RXTX = 3,
46 };
47
48 enum {
49 SYSCLK_156250 = 2,
50 };
51
52 enum {
53 RAM_NONE = 0,
54 RAM_DDR2_32 = 1,
55 RAM_DDR2_64 = 2,
56 };
57
58 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
59
misc_init_r(void)60 int misc_init_r(void)
61 {
62 /* startup fans */
63 dtt_init();
64
65 return 0;
66 }
67
get_hwver(void)68 static unsigned int get_hwver(void)
69 {
70 u16 latch3 = in_le16((void *)LATCH3_BASE);
71
72 return latch3 & 0x0003;
73 }
74
get_mc2_present(void)75 static unsigned int get_mc2_present(void)
76 {
77 u16 latch2 = in_le16((void *)LATCH2_BASE);
78
79 return !(latch2 & LATCH2_MC2_PRESENT_N);
80 }
81
print_fpga_info(unsigned dev)82 static void print_fpga_info(unsigned dev)
83 {
84 u16 versions;
85 u16 fpga_version;
86 u16 fpga_features;
87 unsigned unit_type;
88 unsigned hardware_version;
89 unsigned feature_rs232;
90 unsigned feature_audio;
91 unsigned feature_sysclock;
92 unsigned feature_ramconfig;
93 unsigned feature_carrier_speed;
94 unsigned feature_carriers;
95 unsigned feature_video_channels;
96 int fpga_state = get_fpga_state(dev);
97
98 printf("FPGA%d: ", dev);
99
100 FPGA_GET_REG(dev, versions, &versions);
101 FPGA_GET_REG(dev, fpga_version, &fpga_version);
102 FPGA_GET_REG(dev, fpga_features, &fpga_features);
103
104 hardware_version = versions & 0x000f;
105
106 if (fpga_state
107 && !((hardware_version == HWVER_101)
108 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
109 puts("not available\n");
110 print_fpga_state(dev);
111 return;
112 }
113
114 unit_type = (versions >> 4) & 0x000f;
115 hardware_version = versions & 0x000f;
116 feature_rs232 = fpga_features & (1<<11);
117 feature_audio = (fpga_features >> 9) & 0x0003;
118 feature_sysclock = (fpga_features >> 7) & 0x0003;
119 feature_ramconfig = (fpga_features >> 5) & 0x0003;
120 feature_carrier_speed = fpga_features & (1<<4);
121 feature_carriers = (fpga_features >> 2) & 0x0003;
122 feature_video_channels = fpga_features & 0x0003;
123
124 switch (unit_type) {
125 case UNITTYPE_VIDEO_USER:
126 printf("Videochannel Userside");
127 break;
128
129 case UNITTYPE_MAIN_USER:
130 printf("Mainchannel Userside");
131 break;
132
133 case UNITTYPE_VIDEO_SERVER:
134 printf("Videochannel Serverside");
135 break;
136
137 case UNITTYPE_MAIN_SERVER:
138 printf("Mainchannel Serverside");
139 break;
140
141 default:
142 printf("UnitType %d(not supported)", unit_type);
143 break;
144 }
145
146 switch (hardware_version) {
147 case HWVER_101:
148 printf(" HW-Ver 1.01\n");
149 break;
150
151 case HWVER_110:
152 printf(" HW-Ver 1.10-1.12\n");
153 break;
154
155 case HWVER_120:
156 printf(" HW-Ver 1.20\n");
157 break;
158
159 case HWVER_130:
160 printf(" HW-Ver 1.30\n");
161 break;
162
163 default:
164 printf(" HW-Ver %d(not supported)\n",
165 hardware_version);
166 break;
167 }
168
169 printf(" FPGA V %d.%02d, features:",
170 fpga_version / 100, fpga_version % 100);
171
172 printf(" %sRS232", feature_rs232 ? "" : "no ");
173
174 switch (feature_audio) {
175 case AUDIO_NONE:
176 printf(", no audio");
177 break;
178
179 case AUDIO_TX:
180 printf(", audio tx");
181 break;
182
183 case AUDIO_RX:
184 printf(", audio rx");
185 break;
186
187 case AUDIO_RXTX:
188 printf(", audio rx+tx");
189 break;
190
191 default:
192 printf(", audio %d(not supported)", feature_audio);
193 break;
194 }
195
196 switch (feature_sysclock) {
197 case SYSCLK_156250:
198 printf(", clock 156.25 MHz");
199 break;
200
201 default:
202 printf(", clock %d(not supported)", feature_sysclock);
203 break;
204 }
205
206 puts(",\n ");
207
208 switch (feature_ramconfig) {
209 case RAM_NONE:
210 printf("no RAM");
211 break;
212
213 case RAM_DDR2_32:
214 printf("RAM 32 bit DDR2");
215 break;
216
217 case RAM_DDR2_64:
218 printf("RAM 64 bit DDR2");
219 break;
220
221 default:
222 printf("RAM %d(not supported)", feature_ramconfig);
223 break;
224 }
225
226 printf(", %d carrier(s) %s", feature_carriers,
227 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
228
229 printf(", %d video channel(s)\n", feature_video_channels);
230 }
231
232 /*
233 * Check Board Identity:
234 */
checkboard(void)235 int checkboard(void)
236 {
237 char *s = getenv("serial#");
238
239 puts("Board: ");
240
241 puts("DLVision 10G");
242
243 if (s != NULL) {
244 puts(", serial# ");
245 puts(s);
246 }
247
248 puts("\n");
249
250 return 0;
251 }
252
last_stage_init(void)253 int last_stage_init(void)
254 {
255 u16 versions;
256
257 FPGA_GET_REG(0, versions, &versions);
258
259 print_fpga_info(0);
260 if (get_mc2_present())
261 print_fpga_info(1);
262
263 if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
264 return 0;
265
266 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
267 osd_probe(0);
268
269 if (get_mc2_present() &&
270 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
271 osd_probe(1);
272
273 return 0;
274 }
275
gd405ep_init(void)276 void gd405ep_init(void)
277 {
278 }
279
gd405ep_set_fpga_reset(unsigned state)280 void gd405ep_set_fpga_reset(unsigned state)
281 {
282 if (state) {
283 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
284 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
285 } else {
286 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
287 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
288 }
289 }
290
gd405ep_setup_hw(void)291 void gd405ep_setup_hw(void)
292 {
293 /*
294 * set "startup-finished"-gpios
295 */
296 gpio_write_bit(21, 0);
297 gpio_write_bit(22, 1);
298 }
299
gd405ep_get_fpga_done(unsigned fpga)300 int gd405ep_get_fpga_done(unsigned fpga)
301 {
302 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
303 }
304