1 /* 2 * (C) Copyright 2001 3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 /**************************************************************************** 8 * Global routines used for PIP405 9 *****************************************************************************/ 10 11 #ifndef __ASSEMBLY__ 12 13 extern int mem_test(unsigned long start, unsigned long ramsize,int mode); 14 15 void print_pip405_info(void); 16 17 void user_led0(unsigned char on); 18 void user_led1(unsigned char on); 19 20 21 #define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800 22 #define PLD_PART_REG PLD_BASE_ADDRESS + 0 23 #define PLD_VERS_REG PLD_BASE_ADDRESS + 1 24 #define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2 25 #define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3 26 #define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4 27 #define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5 28 #define PLD_CAN_REG PLD_BASE_ADDRESS + 6 29 #define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7 30 #define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8 31 #define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9 32 #define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA 33 34 #define PIIX4_VENDOR_ID 0x8086 35 #define PIIX4_IDE_DEV_ID 0x7111 36 37 #endif 38 39 /* timings */ 40 41 /* CS Config register (CS7) */ 42 #define CONFIG_PORT_BME 0 /* Burst disable */ 43 #define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ 44 #define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 45 #define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ 46 #define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */ 47 #define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */ 48 #define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */ 49 #define CONFIG_PORT_RE 0 /* Ready disabled */ 50 #define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ 51 #define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ 52 #define CONFIG_PORT_PEN 0 /* Parity disable */ 53 #define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ 54 (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) 55 56 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 57 #define CONFIG_PORT_BS 0 /* 1 MByte */ 58 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 59 #define CONFIG_PORT_BU 3 /* R/W */ 60 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 61 #define CONFIG_PORT_BW 0 /* 16Bit */ 62 #define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13)) 63 64 /* Flash CS0 or CS 1 */ 65 /* 0x7F8FFE80 slowest timing at all... */ 66 #define FLASH_BME_B 1 /* Burst enable */ 67 #define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ 68 #define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ 69 #define FLASH_BME 0 /* Burst disable */ 70 #define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ 71 #define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 72 #define FLASH_OEN 1 /* Cycles from CS low to OE low */ 73 #define FLASH_WBN 1 /* Cycles from CS low to WE low */ 74 #define FLASH_WBF 1 /* Cycles from WE high to CS high */ 75 #define FLASH_TH 2 /* Number of hold cycles after transfer */ 76 #define FLASH_RE 0 /* Ready disabled */ 77 #define FLASH_SOR 1 /* Sample on Ready disabled */ 78 #define FLASH_BEM 0 /* Byte Write only active on Write cycles */ 79 #define FLASH_PEN 0 /* Parity disable */ 80 /* Access Parameter Register for non Boot */ 81 #define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ 82 (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) 83 /* Access Parameter Register for Boot */ 84 #define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ 85 (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) 86 87 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 88 #define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ 89 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 90 #define FLASH_BU 3 /* R/W */ 91 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 92 #define FLASH_BW 1 /* 16Bit */ 93 /* CR register for Boot */ 94 #define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) 95 /* CR register for non Boot */ 96 #define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) 97 98 /* MPS CS1 or CS0 */ 99 /* Boot CS: */ 100 #define MPS_BME_B 1 /* Burst enable */ 101 #define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ 102 #define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ 103 #define MPS_BME 0 /* Burst disable */ 104 #define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ 105 #define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 106 #define MPS_OEN 1 /* Cycles from CS low to OE low */ 107 #define MPS_WBN 1 /* Cycles from CS low to WE low */ 108 #define MPS_WBF 1 /* Cycles from WE high to CS high */ 109 #define MPS_TH 2 /* Number of hold cycles after transfer */ 110 #define MPS_RE 0 /* Ready disabled */ 111 #define MPS_SOR 1 /* Sample on Ready disabled */ 112 #define MPS_BEM 0 /* Byte Write only active on Write cycles */ 113 #define MPS_PEN 0 /* Parity disable */ 114 /* Access Parameter Register for non Boot */ 115 #define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ 116 (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) 117 /* Access Parameter Register for Boot */ 118 #define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ 119 (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) 120 121 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 122 #define MPS_BS 2 /* 4 MByte */ 123 #define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ 124 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 125 #define MPS_BU 3 /* R/W */ 126 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 127 #define MPS_BW 0 /* 8Bit */ 128 /* CR register for Boot */ 129 #define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) 130 /* CR register for non Boot */ 131 #define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) 132