1 /* 2 * (C) Copyright 2006-2008 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /*----------------------------------------------------------------------- 12 * High Level Configuration Options 13 *----------------------------------------------------------------------*/ 14 #define CONFIG_ALPR 1 /* Board is ebony */ 15 #define CONFIG_440GX 1 /* Specifc GX support */ 16 #define CONFIG_440 1 /* ... PPC440 family */ 17 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 18 #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 21 22 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ 23 #define CONFIG_4xx_DCACHE /* Enable i- and d-cache */ 24 25 /*----------------------------------------------------------------------- 26 * Base addresses -- Note these are effective addresses where the 27 * actual resources get mapped (not physical addresses) 28 *----------------------------------------------------------------------*/ 29 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ 30 #define CONFIG_SYS_FLASH_BASE 0xffe00000 /* start of FLASH */ 31 #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ 32 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ 33 #define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ 34 #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ 35 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ 36 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 37 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 38 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 39 40 41 #define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000) 42 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) 43 44 /*----------------------------------------------------------------------- 45 * Initial RAM & stack pointer (placed in internal SRAM) 46 *----------------------------------------------------------------------*/ 47 #define CONFIG_SYS_TEMP_STACK_OCM 1 48 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE 49 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ 50 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ 51 52 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 53 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) 54 55 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 56 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ 57 58 /*----------------------------------------------------------------------- 59 * Serial Port 60 *----------------------------------------------------------------------*/ 61 #define CONFIG_CONS_INDEX 2 /* Use UART1 */ 62 #define CONFIG_SYS_NS16550 63 #define CONFIG_SYS_NS16550_SERIAL 64 #define CONFIG_SYS_NS16550_REG_SIZE 1 65 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 66 67 #undef CONFIG_SYS_EXT_SERIAL_CLOCK 68 #define CONFIG_BAUDRATE 115200 69 70 #define CONFIG_SYS_BAUDRATE_TABLE \ 71 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 72 73 /*----------------------------------------------------------------------- 74 * FLASH related 75 *----------------------------------------------------------------------*/ 76 #define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */ 77 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ 78 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 79 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 80 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 81 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 82 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ 83 84 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 85 86 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ 87 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 88 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 89 90 /* Address and size of Redundant Environment Sector */ 91 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 92 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 93 94 /*----------------------------------------------------------------------- 95 * DDR SDRAM 96 *----------------------------------------------------------------------*/ 97 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ 98 #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ 99 #undef CONFIG_SDRAM_ECC /* enable ECC support */ 100 #define CONFIG_SYS_SDRAM_TABLE { \ 101 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ 102 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ 103 104 /*----------------------------------------------------------------------- 105 * I2C 106 *----------------------------------------------------------------------*/ 107 #define CONFIG_SYS_I2C 108 #define CONFIG_SYS_I2C_PPC4XX 109 #define CONFIG_SYS_I2C_PPC4XX_CH0 110 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 111 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F 112 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 113 114 /*----------------------------------------------------------------------- 115 * I2C EEPROM (PCF8594C) 116 *----------------------------------------------------------------------*/ 117 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ 118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 119 /* mask of address bits that overflow into the "EEPROM chip address" */ 120 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 121 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ 122 /* 8 byte page write mode using */ 123 /* last 3 bits of the address */ 124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ 125 126 #define CONFIG_PREBOOT "echo;" \ 127 "echo Type \"run kernelx\" to boot the system;" \ 128 "echo" 129 130 #undef CONFIG_BOOTARGS 131 132 #define CONFIG_EXTRA_ENV_SETTINGS \ 133 "netdev=eth3\0" \ 134 "hostname=alpr\0" \ 135 "fdt_file=alpr/alpr.dtb\0" \ 136 "fdt_addr=400000\0" \ 137 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 138 "nfsroot=${serverip}:${rootpath} ${init}\0" \ 139 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 140 "addip=setenv bootargs ${bootargs} " \ 141 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 142 ":${hostname}:${netdev}:off panic=1\0" \ 143 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ 144 "mem=193M\0" \ 145 "flash_nfs=run nfsargs addip addtty;" \ 146 "bootm ${kernel_addr}\0" \ 147 "flash_self=run ramargs addip addtty;" \ 148 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 149 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 150 "bootm\0" \ 151 "net_nfs_fdt=tftp 200000 ${bootfile};" \ 152 "tftp ${fdt_addr} ${fdt_file};" \ 153 "run nfsargs addip addtty;" \ 154 "bootm 200000 - ${fdt_addr}\0" \ 155 "rootpath=/opt/projects/alpr/nfs_root\0" \ 156 "bootfile=/alpr/uImage\0" \ 157 "kernel_addr=fff00000\0" \ 158 "ramdisk_addr=fff10000\0" \ 159 "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ 160 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ 161 "cp.b 100000 fffc0000 40000;" \ 162 "setenv filesize;saveenv\0" \ 163 "upd=run load update\0" \ 164 "ethprime=ppc_4xx_eth3\0" \ 165 "ethact=ppc_4xx_eth3\0" \ 166 "autoload=no\0" \ 167 "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ 168 "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ 169 "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ 170 "rootfstype=jffs2 init=/sbin/init\0" \ 171 "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ 172 ";bootm 200000\0" \ 173 "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ 174 "addtty;bootm 200000\0" \ 175 "kernel1=setenv actkernel 'kernel1';run load_fpga " \ 176 "kernel1_mtd\0" \ 177 "kernel2=setenv actkernel 'kernel2';run load_fpga " \ 178 "kernel2_mtd\0" \ 179 "" 180 181 #define CONFIG_BOOTCOMMAND "run kernel2" 182 183 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ 184 185 #define CONFIG_BAUDRATE 115200 186 187 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 188 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 189 190 #define CONFIG_PPC4xx_EMAC 191 #define CONFIG_MII 1 /* MII PHY management */ 192 #define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ 193 #define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ 194 #define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ 195 #define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ 196 #define CONFIG_HAS_ETH0 197 #define CONFIG_HAS_ETH1 198 #define CONFIG_HAS_ETH2 199 #define CONFIG_HAS_ETH3 200 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ 201 #define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ 202 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 203 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ 204 205 #define CONFIG_NETCONSOLE /* include NetConsole support */ 206 207 208 /* 209 * BOOTP options 210 */ 211 #define CONFIG_BOOTP_BOOTFILESIZE 212 #define CONFIG_BOOTP_BOOTPATH 213 #define CONFIG_BOOTP_GATEWAY 214 #define CONFIG_BOOTP_HOSTNAME 215 216 217 /* 218 * Command line configuration. 219 */ 220 #define CONFIG_CMD_DHCP 221 #define CONFIG_CMD_EEPROM 222 #define CONFIG_CMD_FPGA_LOADMK 223 #define CONFIG_CMD_I2C 224 #define CONFIG_CMD_MII 225 #define CONFIG_CMD_NAND 226 #define CONFIG_CMD_PCI 227 228 #undef CONFIG_WATCHDOG /* watchdog disabled */ 229 230 /* 231 * Miscellaneous configurable options 232 */ 233 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 234 #if defined(CONFIG_CMD_KGDB) 235 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 236 #else 237 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 238 #endif 239 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 240 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 241 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 242 243 #define CONFIG_SYS_ALT_MEMTEST 1 /* Enable more extensive memtest*/ 244 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 245 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 246 247 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 248 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 249 250 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 251 #define CONFIG_LOOPW 1 /* enable loopw command */ 252 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 253 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 254 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 255 256 #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ 257 258 /*----------------------------------------------------------------------- 259 * PCI stuff 260 *----------------------------------------------------------------------- 261 */ 262 /* General PCI */ 263 #define CONFIG_PCI /* include pci support */ 264 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 265 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 266 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 267 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ 268 #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ 269 270 /* Board-specific PCI */ 271 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ 272 #define CONFIG_SYS_PCI_MASTER_INIT 273 274 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ 275 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ 276 277 /*----------------------------------------------------------------------- 278 * FPGA stuff 279 *-----------------------------------------------------------------------*/ 280 #define CONFIG_FPGA 281 #define CONFIG_FPGA_ALTERA 282 #define CONFIG_FPGA_CYCLON2 283 #define CONFIG_SYS_FPGA_CHECK_CTRLC 284 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 285 #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in 286 Reihe geschaltet -> sollte gehen, 287 aufpassen mit Datasize ist jetzt 288 halt doppelt so gross ... Seite 306 289 ist das mit den multiple Device in PS 290 Mode erklaert ...*/ 291 292 /* FPGA program pin configuration */ 293 #define CONFIG_SYS_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ 294 #define CONFIG_SYS_GPIO_DATA 19 /* FPGA data pin (cpu output) */ 295 #define CONFIG_SYS_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ 296 #define CONFIG_SYS_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ 297 #define CONFIG_SYS_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ 298 299 #define CONFIG_SYS_GPIO_SEL_DPR 14 /* cpu output */ 300 #define CONFIG_SYS_GPIO_SEL_AVR 15 /* cpu output */ 301 #define CONFIG_SYS_GPIO_PROG_EN 23 /* cpu output */ 302 303 /*----------------------------------------------------------------------- 304 * Definitions for GPIO setup 305 *-----------------------------------------------------------------------*/ 306 #define CONFIG_SYS_GPIO_SHUTDOWN (0x80000000 >> 6) 307 #define CONFIG_SYS_GPIO_SSD_EMPTY (0x80000000 >> 9) 308 #define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 26) 309 #define CONFIG_SYS_GPIO_REV0 (0x80000000 >> 14) 310 #define CONFIG_SYS_GPIO_REV1 (0x80000000 >> 15) 311 312 /*----------------------------------------------------------------------- 313 * NAND-FLASH stuff 314 *-----------------------------------------------------------------------*/ 315 #define CONFIG_SYS_MAX_NAND_DEVICE 4 316 #define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ 317 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ 318 CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } 319 #define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ 320 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 321 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 322 323 /*----------------------------------------------------------------------- 324 * External Bus Controller (EBC) Setup 325 *----------------------------------------------------------------------*/ 326 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE 327 328 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ 329 #define CONFIG_SYS_EBC_PB0AP 0x92015480 330 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ 331 332 /* Memory Bank 1 (NAND-FLASH) initialization */ 333 #define CONFIG_SYS_EBC_PB1AP 0x01840380 /* TWT=3 */ 334 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ 335 336 /* 337 * For booting Linux, the board info and command line data 338 * have to be in the first 8 MB of memory, since this is 339 * the maximum mapped by the Linux kernel during initialization. 340 */ 341 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 342 343 #if defined(CONFIG_CMD_KGDB) 344 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 345 #endif 346 347 /* pass open firmware flat tree */ 348 #define CONFIG_OF_LIBFDT 1 349 #define CONFIG_OF_BOARD_SETUP 1 350 351 #endif /* __CONFIG_H */ 352