1 /* 2 * (C) Copyright 2008 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * Based on include/configs/yosemite.h 6 * (C) Copyright 2005-2007 7 * Stefan Roese, DENX Software Engineering, sr@denx.de. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 /* 13 * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module 14 */ 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * High Level Configuration Options 20 */ 21 #define CONFIG_440GR 1 /* Specific PPC440GR support */ 22 #define CONFIG_HOSTNAME gdppc440etx 23 #define CONFIG_440 1 /* ... PPC440 family */ 24 #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ 25 26 #define CONFIG_SYS_TEXT_BASE 0xFFF80000 27 28 /* 29 * Include common defines/options for all AMCC eval boards 30 */ 31 #include "amcc-common.h" 32 33 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ 34 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ 35 #define CONFIG_SYS_GENERIC_BOARD 36 37 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 38 39 /* 40 * Base addresses -- Note these are effective addresses where the 41 * actual resources get mapped (not physical addresses) 42 */ 43 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ 44 #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ 45 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 46 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 47 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 48 49 /*Don't change either of these*/ 50 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ 51 /*Don't change either of these*/ 52 53 #define CONFIG_SYS_USB_DEVICE 0x50000000 54 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 55 56 /* 57 * Initial RAM & stack pointer (placed in SDRAM) 58 */ 59 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ 60 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ 61 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) 62 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 63 - GENERATED_GBL_DATA_SIZE) 64 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 65 66 /* 67 * Serial Port 68 */ 69 #define CONFIG_CONS_INDEX 2 /* Use UART1 */ 70 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE 1 73 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 74 #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ 75 76 /* 77 * Environment 78 * Define here the location of the environment variables (FLASH or EEPROM). 79 * Note: DENX encourages to use redundant environment in FLASH. 80 */ 81 #define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ 82 83 /* 84 * FLASH related 85 */ 86 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ 87 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 88 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ 89 90 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 91 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ 92 93 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ 94 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ 95 96 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ 97 98 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 99 100 #ifdef CONFIG_ENV_IS_IN_FLASH 101 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ 104 105 /* Address and size of Redundant Environment Sector */ 106 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 107 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 108 #endif /* CONFIG_ENV_IS_IN_FLASH */ 109 110 /* 111 * DDR SDRAM 112 */ 113 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ 114 #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ 115 #define CONFIG_SYS_SDRAM_BANKS (2) 116 117 #define CONFIG_SDRAM_BANK0 118 #define CONFIG_SDRAM_BANK1 119 120 #define CONFIG_SYS_SDRAM0_TR0 0x410a4012 121 #define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 122 #define CONFIG_SYS_SDRAM0_RTR 0x04080000 123 #define CONFIG_SYS_SDRAM0_CFG0 0x80000000 124 125 #undef CONFIG_SDRAM_ECC 126 127 /* 128 * I2C 129 */ 130 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 131 132 /* 133 * Default environment variables 134 */ 135 #define CONFIG_EXTRA_ENV_SETTINGS \ 136 CONFIG_AMCC_DEF_ENV \ 137 CONFIG_AMCC_DEF_ENV_POWERPC \ 138 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 139 "kernel_addr=fc000000\0" \ 140 "ramdisk_addr=fc180000\0" \ 141 "" 142 143 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ 144 #define CONFIG_PHY_ADDR 1 145 #define CONFIG_PHY1_ADDR 3 146 147 #ifdef DEBUG 148 #define CONFIG_PANIC_HANG 149 #endif 150 151 /* 152 * Commands additional to the ones defined in amcc-common.h 153 */ 154 #define CONFIG_CMD_PCI 155 #undef CONFIG_CMD_EEPROM 156 157 /* 158 * PCI stuff 159 */ 160 161 /* General PCI */ 162 #define CONFIG_PCI /* include pci support */ 163 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 164 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ 165 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ 166 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ 167 CONFIG_SYS_PCI_MEMBASE*/ 168 169 /* Board-specific PCI */ 170 #define CONFIG_SYS_PCI_TARGET_INIT 171 #define CONFIG_SYS_PCI_MASTER_INIT 172 173 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ 174 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ 175 176 /* 177 * External Bus Controller (EBC) Setup 178 */ 179 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE 180 181 /* Memory Bank 0 (NOR-FLASH) initialization */ 182 #define CONFIG_SYS_EBC_PB0AP 0x03017200 183 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) 184 185 #endif /* __CONFIG_H */ 186