1 /* 2 * (C) Copyright 2010 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #define CONFIG_405EP 1 /* this is a PPC405 CPU */ 12 #define CONFIG_IO 1 /* on a Io board */ 13 14 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 15 16 /* 17 * Include common defines/options for all AMCC eval boards 18 */ 19 #define CONFIG_HOSTNAME io 20 #define CONFIG_IDENT_STRING " io 0.06" 21 #include "amcc-common.h" 22 23 #define CONFIG_BOARD_EARLY_INIT_F 24 #define CONFIG_BOARD_EARLY_INIT_R 25 #define CONFIG_MISC_INIT_R 26 #define CONFIG_LAST_STAGE_INIT 27 #define CONFIG_SYS_GENERIC_BOARD 28 29 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 30 31 /* 32 * Configure PLL 33 */ 34 #define PLLMR0_DEFAULT PLLMR0_266_133_66 35 #define PLLMR1_DEFAULT PLLMR1_266_133_66 36 37 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 38 39 /* new uImage format support */ 40 #define CONFIG_FIT 41 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 42 #define CONFIG_FIT_DISABLE_SHA256 43 44 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ 45 46 /* 47 * Default environment variables 48 */ 49 #define CONFIG_EXTRA_ENV_SETTINGS \ 50 CONFIG_AMCC_DEF_ENV \ 51 CONFIG_AMCC_DEF_ENV_POWERPC \ 52 CONFIG_AMCC_DEF_ENV_NOR_UPD \ 53 "kernel_addr=fc000000\0" \ 54 "fdt_addr=fc1e0000\0" \ 55 "ramdisk_addr=fc200000\0" \ 56 "" 57 58 #define CONFIG_PHY_ADDR 4 /* PHY address */ 59 #define CONFIG_HAS_ETH0 60 #define CONFIG_HAS_ETH1 61 #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ 62 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ 63 64 /* 65 * Commands additional to the ones defined in amcc-common.h 66 */ 67 #define CONFIG_CMD_DTT 68 #undef CONFIG_CMD_DHCP 69 #undef CONFIG_CMD_DIAG 70 #undef CONFIG_CMD_EEPROM 71 #undef CONFIG_CMD_ELF 72 #undef CONFIG_CMD_I2C 73 #undef CONFIG_CMD_IRQ 74 75 /* 76 * SDRAM configuration (please see cpu/ppc/sdram.[ch]) 77 */ 78 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 79 80 /* SDRAM timings used in datasheet */ 81 #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ 82 #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ 83 #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ 84 #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ 85 #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ 86 87 /* 88 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 89 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 90 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. 91 * The Linux BASE_BAUD define should match this configuration. 92 * baseBaud = cpuClock/(uartDivisor*16) 93 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 94 * set Linux BASE_BAUD to 403200. 95 */ 96 #define CONFIG_CONS_INDEX 1 /* Use UART0 */ 97 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 98 #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 99 #define CONFIG_SYS_BASE_BAUD 691200 100 101 /* 102 * I2C stuff 103 */ 104 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 105 106 /* Temp sensor/hwmon/dtt */ 107 #define CONFIG_DTT_LM63 1 /* National LM63 */ 108 #define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ 109 #define CONFIG_DTT_PWM_LOOKUPTABLE \ 110 { { 40, 10 }, { 50, 20 }, { 60, 40 } } 111 #define CONFIG_DTT_TACH_LIMIT 0xa10 112 113 /* 114 * FLASH organization 115 */ 116 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 117 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 118 119 #define CONFIG_SYS_FLASH_BASE 0xFC000000 120 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 121 122 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 123 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ 124 125 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ 126 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ 127 128 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ 129 130 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ 131 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ 132 133 #ifdef CONFIG_ENV_IS_IN_FLASH 134 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ 135 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) 136 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 137 138 /* Address and size of Redundant Environment Sector */ 139 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 140 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 141 #endif 142 143 /* Gbit PHYs */ 144 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 145 #define CONFIG_BITBANGMII_MULTI 146 147 #define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */ 148 #define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */ 149 150 #define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy" 151 152 /* 153 * PPC405 GPIO Configuration 154 */ 155 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ 156 { \ 157 /* GPIO Core 0 */ \ 158 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ 159 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ 160 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ 161 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ 162 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ 163 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ 164 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ 165 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ 166 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ 167 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ 168 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ 169 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ 170 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ 171 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ 172 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ 173 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ 174 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ 175 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ 176 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ 177 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ 178 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ 179 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ 180 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ 181 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ 182 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ 183 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ 184 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ 185 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ 186 { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ 187 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ 188 { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ 189 { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ 190 } \ 191 } 192 193 /* 194 * Definitions for initial stack pointer and data area (in data cache) 195 */ 196 /* use on chip memory (OCM) for temperary stack until sdram is tested */ 197 #define CONFIG_SYS_TEMP_STACK_OCM 1 198 199 /* On Chip Memory location */ 200 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 201 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 202 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ 203 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ 204 205 #define CONFIG_SYS_GBL_DATA_OFFSET \ 206 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) 207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 208 209 /* 210 * External Bus Controller (EBC) Setup 211 */ 212 213 /* Memory Bank 0 (NOR-FLASH) initialization */ 214 #define CONFIG_SYS_EBC_PB0AP 0xa382a880 215 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ 216 #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 217 218 /* Memory Bank 1 (NVRAM) initializatio */ 219 #define CONFIG_SYS_EBC_PB1AP 0x92015480 220 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ 221 #define CONFIG_SYS_EBC_PB1CR 0x7f318000 222 223 /* Memory Bank 2 (FPGA) initialization */ 224 #define CONFIG_SYS_FPGA0_BASE 0x7f100000 225 #define CONFIG_SYS_EBC_PB2AP 0x02025080 226 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ 227 #define CONFIG_SYS_EBC_PB2CR 0x7f11a000 228 229 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 230 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 231 232 #define CONFIG_SYS_FPGA_COUNT 1 233 234 #define CONFIG_SYS_FPGA_PTR \ 235 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE } 236 237 #define CONFIG_SYS_FPGA_COMMON 238 239 /* Memory Bank 3 (Latches) initialization */ 240 #define CONFIG_SYS_LATCH_BASE 0x7f200000 241 #define CONFIG_SYS_EBC_PB3AP 0xa2015480 242 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ 243 #define CONFIG_SYS_EBC_PB3CR 0x7f21a000 244 245 #define CONFIG_SYS_LATCH0_RESET 0xffff 246 #define CONFIG_SYS_LATCH0_BOOT 0xffff 247 #define CONFIG_SYS_LATCH1_RESET 0xffbf 248 #define CONFIG_SYS_LATCH1_BOOT 0xffff 249 250 #endif /* __CONFIG_H */ 251