1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 *
10 * (C) Copyright 2003
11 * Texas Instruments, <www.ti.com>
12 * Kshitij Gupta <Kshitij@ti.com>
13 *
14 * (C) Copyright 2004
15 * ARM Ltd.
16 * Philippe Robin, <philippe.robin@arm.com>
17 */
18
19 #include <common.h>
20 #include <bootstage.h>
21 #include <cpu_func.h>
22 #include <dm.h>
23 #include <env.h>
24 #include <init.h>
25 #include <net.h>
26 #include <netdev.h>
27 #include <asm/global_data.h>
28 #include <asm/io.h>
29 #include <dm/platform_data/serial_pl01x.h>
30 #include "arm-ebi.h"
31 #include "integrator-sc.h"
32 #include <asm/mach-types.h>
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 static const struct pl01x_serial_plat serial_plat = {
37 .base = 0x16000000,
38 #ifdef CONFIG_ARCH_CINTEGRATOR
39 .type = TYPE_PL011,
40 .clock = 14745600,
41 #else
42 .type = TYPE_PL010,
43 .clock = 0, /* Not used for PL010 */
44 #endif
45 };
46
47 U_BOOT_DRVINFO(integrator_serials) = {
48 .name = "serial_pl01x",
49 .plat = &serial_plat,
50 };
51
52 void peripheral_power_enable (void);
53
54 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
show_boot_progress(int progress)55 void show_boot_progress(int progress)
56 {
57 printf("Boot reached stage %d\n", progress);
58 }
59 #endif
60
61 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
62
63 /*
64 * Miscellaneous platform dependent initialisations
65 */
66
board_init(void)67 int board_init (void)
68 {
69 u32 val;
70
71 /* arch number of Integrator Board */
72 #ifdef CONFIG_ARCH_CINTEGRATOR
73 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
74 #else
75 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
76 #endif
77
78 /* adress of boot parameters */
79 gd->bd->bi_boot_params = 0x00000100;
80
81 #ifdef CONFIG_CM_REMAP
82 extern void cm_remap(void);
83 cm_remap(); /* remaps writeable memory to 0x00000000 */
84 #endif
85
86 #ifdef CONFIG_ARCH_CINTEGRATOR
87 /*
88 * Flash protection on the Integrator/CP is in a simple register
89 */
90 val = readl(CP_FLASHPROG);
91 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
92 writel(val, CP_FLASHPROG);
93 #else
94 /*
95 * The Integrator/AP has some special protection mechanisms
96 * for the external memories, first the External Bus Interface (EBI)
97 * then the system controller (SC).
98 *
99 * The system comes up with the flash memory non-writable and
100 * configuration locked. If we want U-Boot to be used for flash
101 * access we cannot have the flash memory locked.
102 */
103 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
104 val = readl(EBI_BASE + EBI_CSR1_REG);
105 val &= EBI_CSR_WREN_MASK;
106 val |= EBI_CSR_WREN_ENABLE;
107 writel(val, EBI_BASE + EBI_CSR1_REG);
108 writel(0, EBI_BASE + EBI_LOCK_REG);
109
110 /*
111 * Set up the system controller to remove write protection from
112 * the flash memory and enable Vpp
113 */
114 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
115 #endif
116
117 icache_enable();
118
119 return 0;
120 }
121
misc_init_r(void)122 int misc_init_r (void)
123 {
124 env_set("verify", "n");
125 return (0);
126 }
127
128 /*
129 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
130 * from there, which means we cannot test the RAM underneath the ROM at this
131 * point. It will be unmapped later on, when we are executing from the
132 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
133 * RAM on higher addresses works fine.
134 */
135 #define REMAPPED_FLASH_SZ 0x40000
136
dram_init(void)137 int dram_init (void)
138 {
139 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
140 #ifdef CONFIG_CM_SPD_DETECT
141 {
142 extern void dram_query(void);
143 u32 cm_reg_sdram;
144 u32 sdram_shift;
145
146 dram_query(); /* Assembler accesses to CM registers */
147 /* Queries the SPD values */
148
149 /* Obtain the SDRAM size from the CM SDRAM register */
150
151 cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
152 /* Register SDRAM size
153 *
154 * 0xXXXXXXbbb000bb 16 MB
155 * 0xXXXXXXbbb001bb 32 MB
156 * 0xXXXXXXbbb010bb 64 MB
157 * 0xXXXXXXbbb011bb 128 MB
158 * 0xXXXXXXbbb100bb 256 MB
159 *
160 */
161 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
162 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
163 REMAPPED_FLASH_SZ,
164 0x01000000 << sdram_shift);
165 }
166 #else
167 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
168 REMAPPED_FLASH_SZ,
169 PHYS_SDRAM_1_SIZE);
170 #endif /* CM_SPD_DETECT */
171 /* We only have one bank of RAM, set it to whatever was detected */
172 gd->bd->bi_dram[0].size = gd->ram_size;
173
174 return 0;
175 }
176
177 #ifdef CONFIG_CMD_NET
board_eth_init(struct bd_info * bis)178 int board_eth_init(struct bd_info *bis)
179 {
180 int rc = 0;
181 #ifdef CONFIG_SMC91111
182 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
183 #endif
184 rc += pci_eth_init(bis);
185 return rc;
186 }
187 #endif
188