1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * P2041 RDB board configuration file 9 * Also supports P2040 RDB 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 17 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 18 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg 19 #endif 20 21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 22 /* Set 1M boot space */ 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #endif 28 29 /* High Level Configuration Options */ 30 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 37 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 38 #define CONFIG_PCIE1 /* PCIE controller 1 */ 39 #define CONFIG_PCIE2 /* PCIE controller 2 */ 40 #define CONFIG_PCIE3 /* PCIE controller 3 */ 41 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 42 43 #define CONFIG_SYS_SRIO 44 #define CONFIG_SRIO1 /* SRIO port 1 */ 45 #define CONFIG_SRIO2 /* SRIO port 2 */ 46 #define CONFIG_SRIO_PCIE_BOOT_MASTER 47 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 48 49 #if defined(CONFIG_SPIFLASH) 50 #elif defined(CONFIG_SDCARD) 51 #define CONFIG_FSL_FIXED_MMC_LOCATION 52 #endif 53 54 #ifndef __ASSEMBLY__ 55 unsigned long get_board_sys_clk(unsigned long dummy); 56 #include <linux/stringify.h> 57 #endif 58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_SYS_CACHE_STASHING 64 #define CONFIG_BACKSIDE_L2_CACHE 65 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #define CONFIG_ENABLE_36BIT_PHYS 69 70 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 71 72 /* 73 * Config the L3 Cache as L3 SRAM 74 */ 75 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 76 #ifdef CONFIG_PHYS_64BIT 77 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ 78 CONFIG_RAMBOOT_TEXT_BASE) 79 #else 80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 81 #endif 82 #define CONFIG_SYS_L3_SIZE (1024 << 10) 83 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 84 85 #ifdef CONFIG_PHYS_64BIT 86 #define CONFIG_SYS_DCSRBAR 0xf0000000 87 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 88 #endif 89 90 /* EEPROM */ 91 #define CONFIG_ID_EEPROM 92 #define CONFIG_SYS_I2C_EEPROM_NXID 93 #define CONFIG_SYS_EEPROM_BUS_NUM 0 94 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 95 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 96 97 /* 98 * DDR Setup 99 */ 100 #define CONFIG_VERY_BIG_RAM 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 104 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 105 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 106 107 #define CONFIG_DDR_SPD 108 109 #define CONFIG_SYS_SPD_BUS_NUM 0 110 #define SPD_EEPROM_ADDRESS 0x52 111 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 112 113 /* 114 * Local Bus Definitions 115 */ 116 117 /* Set the local bus clock 1/8 of platform clock */ 118 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 119 120 /* 121 * This board doesn't have a promjet connector. 122 * However, it uses commone corenet board LAW and TLB. 123 * It is necessary to use the same start address with proper offset. 124 */ 125 #define CONFIG_SYS_FLASH_BASE 0xe0000000 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 128 #else 129 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 130 #endif 131 132 #define CONFIG_SYS_FLASH_BR_PRELIM \ 133 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 134 BR_PS_16 | BR_V) 135 #define CONFIG_SYS_FLASH_OR_PRELIM \ 136 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 137 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 138 139 #define CONFIG_FSL_CPLD 140 #define CPLD_BASE 0xffdf0000 /* CPLD registers */ 141 #ifdef CONFIG_PHYS_64BIT 142 #define CPLD_BASE_PHYS 0xfffdf0000ull 143 #else 144 #define CPLD_BASE_PHYS CPLD_BASE 145 #endif 146 147 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) 148 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 149 150 #define PIXIS_LBMAP_SWITCH 7 151 #define PIXIS_LBMAP_MASK 0xf0 152 #define PIXIS_LBMAP_SHIFT 4 153 #define PIXIS_LBMAP_ALTBANK 0x40 154 155 #define CONFIG_SYS_FLASH_QUIET_TEST 156 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 157 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 159 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 160 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ 161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ 162 163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 164 165 #if defined(CONFIG_RAMBOOT_PBL) 166 #define CONFIG_SYS_RAMBOOT 167 #endif 168 169 #define CONFIG_NAND_FSL_ELBC 170 /* Nand Flash */ 171 #ifdef CONFIG_NAND_FSL_ELBC 172 #define CONFIG_SYS_NAND_BASE 0xffa00000 173 #ifdef CONFIG_PHYS_64BIT 174 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 175 #else 176 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 177 #endif 178 179 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 180 #define CONFIG_SYS_MAX_NAND_DEVICE 1 181 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 182 183 /* NAND flash config */ 184 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 185 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 186 | BR_PS_8 /* Port Size = 8 bit */ \ 187 | BR_MS_FCM /* MSEL = FCM */ \ 188 | BR_V) /* valid */ 189 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 190 | OR_FCM_PGS /* Large Page*/ \ 191 | OR_FCM_CSCT \ 192 | OR_FCM_CST \ 193 | OR_FCM_CHT \ 194 | OR_FCM_SCY_1 \ 195 | OR_FCM_TRLX \ 196 | OR_FCM_EHTR) 197 198 #ifdef CONFIG_MTD_RAW_NAND 199 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 200 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 201 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 202 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 203 #else 204 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 205 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 206 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 207 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 208 #endif 209 #else 210 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 211 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 212 #endif /* CONFIG_NAND_FSL_ELBC */ 213 214 #define CONFIG_SYS_FLASH_EMPTY_INFO 215 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 216 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 217 218 #define CONFIG_HWCONFIG 219 220 /* define to use L1 as initial stack */ 221 #define CONFIG_L1_INIT_RAM 222 #define CONFIG_SYS_INIT_RAM_LOCK 223 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 224 #ifdef CONFIG_PHYS_64BIT 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 227 /* The assembler doesn't like typecast */ 228 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 229 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 230 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 231 #else 232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 233 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 234 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 235 #endif 236 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 237 238 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 239 GENERATED_GBL_DATA_SIZE) 240 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 241 242 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 243 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 244 245 /* Serial Port - controlled on board with jumper J8 246 * open - index 2 247 * shorted - index 1 248 */ 249 #define CONFIG_SYS_NS16550_SERIAL 250 #define CONFIG_SYS_NS16550_REG_SIZE 1 251 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 252 253 #define CONFIG_SYS_BAUDRATE_TABLE \ 254 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 255 256 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 257 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 258 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 259 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 260 261 /* I2C */ 262 #if !CONFIG_IS_ENABLED(DM_I2C) 263 #define CONFIG_SYS_I2C 264 #define CONFIG_SYS_FSL_I2C_SPEED 400000 265 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 266 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 267 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 268 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 269 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 270 #else 271 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 272 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 273 #endif 274 #define CONFIG_SYS_I2C_FSL 275 276 277 /* 278 * RapidIO 279 */ 280 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 281 #ifdef CONFIG_PHYS_64BIT 282 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 283 #else 284 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 285 #endif 286 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 287 288 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 291 #else 292 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 293 #endif 294 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 295 296 /* 297 * for slave u-boot IMAGE instored in master memory space, 298 * PHYS must be aligned based on the SIZE 299 */ 300 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 301 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 302 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 303 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 304 /* 305 * for slave UCODE and ENV instored in master memory space, 306 * PHYS must be aligned based on the SIZE 307 */ 308 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 309 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 310 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 311 312 /* slave core release by master*/ 313 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 314 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 315 316 /* 317 * SRIO_PCIE_BOOT - SLAVE 318 */ 319 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 320 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 321 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 322 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 323 #endif 324 325 /* 326 * eSPI - Enhanced SPI 327 */ 328 329 /* 330 * General PCI 331 * Memory space is mapped 1-1, but I/O space must start from 0. 332 */ 333 334 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 335 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 336 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 337 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 338 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 339 340 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 341 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 342 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 343 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 344 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 345 346 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 347 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 348 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 349 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 350 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 351 352 /* Qman/Bman */ 353 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 354 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 355 #ifdef CONFIG_PHYS_64BIT 356 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 357 #else 358 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 359 #endif 360 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 361 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 362 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 363 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 364 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 365 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 366 CONFIG_SYS_BMAN_CENA_SIZE) 367 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 368 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 369 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 370 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 373 #else 374 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 375 #endif 376 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 377 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 378 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 379 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 380 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 381 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 382 CONFIG_SYS_QMAN_CENA_SIZE) 383 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 384 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 385 386 #define CONFIG_SYS_DPAA_FMAN 387 #define CONFIG_SYS_DPAA_PME 388 /* Default address of microcode for the Linux Fman driver */ 389 #if defined(CONFIG_SPIFLASH) 390 /* 391 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 392 * env, so we got 0x110000. 393 */ 394 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 395 #elif defined(CONFIG_SDCARD) 396 /* 397 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 398 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 399 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 400 */ 401 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 402 #elif defined(CONFIG_MTD_RAW_NAND) 403 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 404 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 405 /* 406 * Slave has no ucode locally, it can fetch this from remote. When implementing 407 * in two corenet boards, slave's ucode could be stored in master's memory 408 * space, the address can be mapped from slave TLB->slave LAW-> 409 * slave SRIO or PCIE outbound window->master inbound window-> 410 * master LAW->the ucode address in master's memory space. 411 */ 412 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 413 #else 414 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 415 #endif 416 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 417 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 418 419 #ifdef CONFIG_PCI 420 #if !defined(CONFIG_DM_PCI) 421 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 422 #define CONFIG_PCI_INDIRECT_BRIDGE 423 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 424 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 425 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 426 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 427 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 429 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 430 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 431 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 432 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 433 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 434 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 435 #endif 436 437 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 438 #endif /* CONFIG_PCI */ 439 440 /* SATA */ 441 #define CONFIG_FSL_SATA_V2 442 443 #ifdef CONFIG_FSL_SATA_V2 444 #define CONFIG_SYS_SATA_MAX_DEVICE 2 445 #define CONFIG_SATA1 446 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 447 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 448 #define CONFIG_SATA2 449 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 450 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 451 452 #define CONFIG_LBA48 453 #endif 454 455 #ifdef CONFIG_FMAN_ENET 456 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 457 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 458 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 459 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 460 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 461 462 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 463 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 464 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 465 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 466 467 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 468 469 #define CONFIG_SYS_TBIPA_VALUE 8 470 #define CONFIG_ETHPRIME "FM1@DTSEC1" 471 #endif 472 473 /* 474 * Environment 475 */ 476 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 477 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 478 479 /* 480 * USB 481 */ 482 #define CONFIG_HAS_FSL_DR_USB 483 #define CONFIG_HAS_FSL_MPH_USB 484 485 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 486 #define CONFIG_USB_EHCI_FSL 487 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 488 #endif 489 490 #ifdef CONFIG_MMC 491 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 492 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 493 #endif 494 495 /* 496 * Miscellaneous configurable options 497 */ 498 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 499 500 /* 501 * For booting Linux, the board info and command line data 502 * have to be in the first 64 MB of memory, since this is 503 * the maximum mapped by the Linux kernel during initialization. 504 */ 505 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ 506 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 507 508 #ifdef CONFIG_CMD_KGDB 509 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 510 #endif 511 512 /* 513 * Environment Configuration 514 */ 515 #define CONFIG_ROOTPATH "/opt/nfsroot" 516 #define CONFIG_BOOTFILE "uImage" 517 #define CONFIG_UBOOTPATH u-boot.bin 518 519 /* default location for tftp and bootm */ 520 #define CONFIG_LOADADDR 1000000 521 522 #define __USB_PHY_TYPE utmi 523 524 #define CONFIG_EXTRA_ENV_SETTINGS \ 525 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 526 "bank_intlv=cs0_cs1\0" \ 527 "netdev=eth0\0" \ 528 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 529 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 530 "tftpflash=tftpboot $loadaddr $uboot && " \ 531 "protect off $ubootaddr +$filesize && " \ 532 "erase $ubootaddr +$filesize && " \ 533 "cp.b $loadaddr $ubootaddr $filesize && " \ 534 "protect on $ubootaddr +$filesize && " \ 535 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 536 "consoledev=ttyS0\0" \ 537 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 538 "usb_dr_mode=host\0" \ 539 "ramdiskaddr=2000000\0" \ 540 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ 541 "fdtaddr=1e00000\0" \ 542 "fdtfile=p2041rdb/p2041rdb.dtb\0" \ 543 "bdev=sda3\0" 544 545 #define CONFIG_HDBOOT \ 546 "setenv bootargs root=/dev/$bdev rw " \ 547 "console=$consoledev,$baudrate $othbootargs;" \ 548 "tftp $loadaddr $bootfile;" \ 549 "tftp $fdtaddr $fdtfile;" \ 550 "bootm $loadaddr - $fdtaddr" 551 552 #define CONFIG_NFSBOOTCOMMAND \ 553 "setenv bootargs root=/dev/nfs rw " \ 554 "nfsroot=$serverip:$rootpath " \ 555 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "tftp $loadaddr $bootfile;" \ 558 "tftp $fdtaddr $fdtfile;" \ 559 "bootm $loadaddr - $fdtaddr" 560 561 #define CONFIG_RAMBOOTCOMMAND \ 562 "setenv bootargs root=/dev/ram rw " \ 563 "console=$consoledev,$baudrate $othbootargs;" \ 564 "tftp $ramdiskaddr $ramdiskfile;" \ 565 "tftp $loadaddr $bootfile;" \ 566 "tftp $fdtaddr $fdtfile;" \ 567 "bootm $loadaddr $ramdiskaddr $fdtaddr" 568 569 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 570 571 #include <asm/fsl_secure_boot.h> 572 573 #endif /* __CONFIG_H */ 574