1 /** @file 2 * 3 * Copyright (c) 2011, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #include <Library/ArmPlatformLib.h> 16 #include <Library/DebugLib.h> 17 #include <Library/PcdLib.h> 18 #include <Library/MemoryAllocationLib.h> 19 #include <Library/IoLib.h> 20 21 #include <ArmPlatform.h> 22 23 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 24 25 // DDR attributes 26 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK 27 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED 28 29 /** 30 Return the Virtual Memory Map of your platform 31 32 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. 33 34 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- 35 Virtual Memory mapping. This array must be ended by a zero-filled 36 entry 37 38 **/ 39 VOID ArmPlatformGetVirtualMemoryMap(IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap)40ArmPlatformGetVirtualMemoryMap ( 41 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap 42 ) 43 { 44 UINT32 CacheAttributes; 45 UINTN Index = 0; 46 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; 47 48 ASSERT(VirtualMemoryMap != NULL); 49 50 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); 51 if (VirtualMemoryTable == NULL) { 52 return; 53 } 54 55 if (FeaturePcdGet(PcdCacheEnable) == TRUE) { 56 CacheAttributes = DDR_ATTRIBUTES_CACHED; 57 } else { 58 CacheAttributes = DDR_ATTRIBUTES_UNCACHED; 59 } 60 61 // ReMap (Either NOR Flash or DRAM) 62 VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE; 63 VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE; 64 VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ; 65 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; 66 67 // DDR 68 VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); 69 VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); 70 VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); 71 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; 72 73 // SMC CS7 74 VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE; 75 VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE; 76 VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ; 77 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 78 79 // SMB CS0-CS1 - NOR Flash 1 & 2 80 VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE; 81 VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE; 82 VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ; 83 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 84 85 // SMB CS2 - SRAM 86 VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE; 87 VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE; 88 VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ; 89 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; 90 91 // SMB CS3-CS6 - Motherboard Peripherals 92 VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE; 93 VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE; 94 VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ; 95 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 96 97 // If a Logic Tile is connected to The ARM Versatile Express Motherboard 98 if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) { 99 VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE; 100 VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE; 101 VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ; 102 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 103 104 ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1)); 105 } else { 106 ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); 107 } 108 109 // End of Table 110 VirtualMemoryTable[++Index].PhysicalBase = 0; 111 VirtualMemoryTable[Index].VirtualBase = 0; 112 VirtualMemoryTable[Index].Length = 0; 113 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; 114 115 *VirtualMemoryMap = VirtualMemoryTable; 116 } 117