1 //! Static, named definitions of instruction opcodes. 2 3 /// Empty opcode for use as a default. 4 pub static EMPTY: [u8; 0] = []; 5 6 /// Add with carry flag r{16,32,64} to r/m of the same size. 7 pub static ADC: [u8; 1] = [0x11]; 8 9 /// Add r{16,32,64} to r/m of the same size. 10 pub static ADD: [u8; 1] = [0x01]; 11 12 /// Add imm{16,32} to r/m{16,32,64}, possibly sign-extended. 13 pub static ADD_IMM: [u8; 1] = [0x81]; 14 15 /// Add sign-extended imm8 to r/m{16,32,64}. 16 pub static ADD_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 17 18 /// Add packed double-precision floating-point values from xmm2/mem to xmm1 and store result in 19 /// xmm1 (SSE2). 20 pub static ADDPD: [u8; 3] = [0x66, 0x0f, 0x58]; 21 22 /// Add packed single-precision floating-point values from xmm2/mem to xmm1 and store result in 23 /// xmm1 (SSE). 24 pub static ADDPS: [u8; 2] = [0x0f, 0x58]; 25 26 /// Add the low double-precision floating-point value from xmm2/mem to xmm1 27 /// and store the result in xmm1. 28 pub static ADDSD: [u8; 3] = [0xf2, 0x0f, 0x58]; 29 30 /// Add the low single-precision floating-point value from xmm2/mem to xmm1 31 /// and store the result in xmm1. 32 pub static ADDSS: [u8; 3] = [0xf3, 0x0f, 0x58]; 33 34 /// r/m{16,32,64} AND register of the same size (Intel docs have a typo). 35 pub static AND: [u8; 1] = [0x21]; 36 37 /// imm{16,32} AND r/m{16,32,64}, possibly sign-extended. 38 pub static AND_IMM: [u8; 1] = [0x81]; 39 40 /// r/m{16,32,64} AND sign-extended imm8. 41 pub static AND_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 42 43 /// Return the bitwise logical AND NOT of packed single-precision floating-point 44 /// values in xmm1 and xmm2/mem. 45 pub static ANDNPS: [u8; 2] = [0x0f, 0x55]; 46 47 /// Return the bitwise logical AND of packed single-precision floating-point values 48 /// in xmm1 and xmm2/mem. 49 pub static ANDPS: [u8; 2] = [0x0f, 0x54]; 50 51 /// Bit scan forward (stores index of first encountered 1 from the front). 52 pub static BIT_SCAN_FORWARD: [u8; 2] = [0x0f, 0xbc]; 53 54 /// Bit scan reverse (stores index of first encountered 1 from the back). 55 pub static BIT_SCAN_REVERSE: [u8; 2] = [0x0f, 0xbd]; 56 57 /// Select packed single-precision floating-point values from xmm1 and xmm2/m128 58 /// from mask specified in XMM0 and store the values into xmm1 (SSE4.1). 59 pub static BLENDVPS: [u8; 4] = [0x66, 0x0f, 0x38, 0x14]; 60 61 /// Select packed double-precision floating-point values from xmm1 and xmm2/m128 62 /// from mask specified in XMM0 and store the values into xmm1 (SSE4.1). 63 pub static BLENDVPD: [u8; 4] = [0x66, 0x0f, 0x38, 0x15]; 64 65 /// Call near, relative, displacement relative to next instruction (sign-extended). 66 pub static CALL_RELATIVE: [u8; 1] = [0xe8]; 67 68 /// Move r/m{16,32,64} if overflow (OF=1). 69 pub static CMOV_OVERFLOW: [u8; 2] = [0x0f, 0x40]; 70 71 /// Compare imm{16,32} with r/m{16,32,64} (sign-extended if 64). 72 pub static CMP_IMM: [u8; 1] = [0x81]; 73 74 /// Compare imm8 with r/m{16,32,64}. 75 pub static CMP_IMM8: [u8; 1] = [0x83]; 76 77 /// Compare r{16,32,64} with r/m of the same size. 78 pub static CMP_REG: [u8; 1] = [0x39]; 79 80 /// Compare packed double-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of 81 /// imm8 as comparison predicate (SSE2). 82 pub static CMPPD: [u8; 3] = [0x66, 0x0f, 0xc2]; 83 84 /// Compare packed single-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of 85 /// imm8 as comparison predicate (SSE). 86 pub static CMPPS: [u8; 2] = [0x0f, 0xc2]; 87 88 /// Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision 89 /// floating-point values in xmm1 (SSE2). 90 pub static CVTDQ2PS: [u8; 2] = [0x0f, 0x5b]; 91 92 /// Convert scalar double-precision floating-point value to scalar single-precision 93 /// floating-point value. 94 pub static CVTSD2SS: [u8; 3] = [0xf2, 0x0f, 0x5a]; 95 96 /// Convert doubleword integer to scalar double-precision floating-point value. 97 pub static CVTSI2SD: [u8; 3] = [0xf2, 0x0f, 0x2a]; 98 99 /// Convert doubleword integer to scalar single-precision floating-point value. 100 pub static CVTSI2SS: [u8; 3] = [0xf3, 0x0f, 0x2a]; 101 102 /// Convert scalar single-precision floating-point value to scalar double-precision 103 /// float-point value. 104 pub static CVTSS2SD: [u8; 3] = [0xf3, 0x0f, 0x5a]; 105 106 /// Convert with truncation scalar double-precision floating-point value to signed 107 /// integer. 108 pub static CVTTSD2SI: [u8; 3] = [0xf2, 0x0f, 0x2c]; 109 110 /// Convert with truncation scalar single-precision floating-point value to integer. 111 pub static CVTTSS2SI: [u8; 3] = [0xf3, 0x0f, 0x2c]; 112 113 /// Unsigned divide for {16,32,64}-bit. 114 pub static DIV: [u8; 1] = [0xf7]; 115 116 /// Divide packed double-precision floating-point values in xmm1 by packed double-precision 117 /// floating-point values in xmm2/mem (SSE2). 118 pub static DIVPD: [u8; 3] = [0x66, 0x0f, 0x5e]; 119 120 /// Divide packed single-precision floating-point values in xmm1 by packed single-precision 121 /// floating-point values in xmm2/mem (SSE). 122 pub static DIVPS: [u8; 2] = [0x0f, 0x5e]; 123 124 /// Divide low double-precision floating-point value in xmm1 by low double-precision 125 /// floating-point value in xmm2/m64. 126 pub static DIVSD: [u8; 3] = [0xf2, 0x0f, 0x5e]; 127 128 /// Divide low single-precision floating-point value in xmm1 by low single-precision 129 /// floating-point value in xmm2/m32. 130 pub static DIVSS: [u8; 3] = [0xf3, 0x0f, 0x5e]; 131 132 /// Signed divide for {16,32,64}-bit. 133 pub static IDIV: [u8; 1] = [0xf7]; 134 135 /// Signed multiply for {16,32,64}-bit, generic registers. 136 pub static IMUL: [u8; 2] = [0x0f, 0xaf]; 137 138 /// Signed multiply for {16,32,64}-bit, storing into RDX:RAX. 139 pub static IMUL_RDX_RAX: [u8; 1] = [0xf7]; 140 141 /// Insert scalar single-precision floating-point value. 142 pub static INSERTPS: [u8; 4] = [0x66, 0x0f, 0x3a, 0x21]; 143 144 /// Either: 145 /// 1. Jump near, absolute indirect, RIP = 64-bit offset from register or memory. 146 /// 2. Jump far, absolute indirect, address given in m16:64. 147 pub static JUMP_ABSOLUTE: [u8; 1] = [0xff]; 148 149 /// Jump near, relative, RIP = RIP + 32-bit displacement sign extended to 64 bits. 150 pub static JUMP_NEAR_RELATIVE: [u8; 1] = [0xe9]; 151 152 /// Jump near (rel32) if overflow (OF=1). 153 pub static JUMP_NEAR_IF_OVERFLOW: [u8; 2] = [0x0f, 0x80]; 154 155 /// Jump short, relative, RIP = RIP + 8-bit displacement sign extended to 64 bits. 156 pub static JUMP_SHORT: [u8; 1] = [0xeb]; 157 158 /// Jump short (rel8) if equal (ZF=1). 159 pub static JUMP_SHORT_IF_EQUAL: [u8; 1] = [0x74]; 160 161 /// Jump short (rel8) if not equal (ZF=0). 162 pub static JUMP_SHORT_IF_NOT_EQUAL: [u8; 1] = [0x75]; 163 164 /// Jump short (rel8) if overflow (OF=1). 165 pub static JUMP_SHORT_IF_OVERFLOW: [u8; 1] = [0x70]; 166 167 /// Store effective address for m in register r{16,32,64}. 168 pub static LEA: [u8; 1] = [0x8d]; 169 170 /// Count the number of leading zero bits. 171 pub static LZCNT: [u8; 3] = [0xf3, 0x0f, 0xbd]; 172 173 /// Return the maximum packed double-precision floating-point values between xmm1 and xmm2/m128 174 /// (SSE2). 175 pub static MAXPD: [u8; 3] = [0x66, 0x0f, 0x5f]; 176 177 /// Return the maximum packed single-precision floating-point values between xmm1 and xmm2/m128 178 /// (SSE). 179 pub static MAXPS: [u8; 2] = [0x0f, 0x5f]; 180 181 /// Return the maximum scalar double-precision floating-point value between 182 /// xmm2/m64 and xmm1. 183 pub static MAXSD: [u8; 3] = [0xf2, 0x0f, 0x5f]; 184 185 /// Return the maximum scalar single-precision floating-point value between 186 /// xmm2/m32 and xmm1. 187 pub static MAXSS: [u8; 3] = [0xf3, 0x0f, 0x5f]; 188 189 /// Return the minimum packed double-precision floating-point values between xmm1 and xmm2/m128 190 /// (SSE2). 191 pub static MINPD: [u8; 3] = [0x66, 0x0f, 0x5d]; 192 193 /// Return the minimum packed single-precision floating-point values between xmm1 and xmm2/m128 194 /// (SSE). 195 pub static MINPS: [u8; 2] = [0x0f, 0x5d]; 196 197 /// Return the minimum scalar double-precision floating-point value between 198 /// xmm2/m64 and xmm1. 199 pub static MINSD: [u8; 3] = [0xf2, 0x0f, 0x5d]; 200 201 /// Return the minimum scalar single-precision floating-point value between 202 /// xmm2/m32 and xmm1. 203 pub static MINSS: [u8; 3] = [0xf3, 0x0f, 0x5d]; 204 205 /// Move r8 to r/m8. 206 pub static MOV_BYTE_STORE: [u8; 1] = [0x88]; 207 208 /// Move imm{16,32,64} to same-sized register. 209 pub static MOV_IMM: [u8; 1] = [0xb8]; 210 211 /// Move imm{16,32} to r{16,32,64}, sign-extended if 64-bit target. 212 pub static MOV_IMM_SIGNEXTEND: [u8; 1] = [0xc7]; 213 214 /// Move {r/m16, r/m32, r/m64} to same-sized register. 215 pub static MOV_LOAD: [u8; 1] = [0x8b]; 216 217 /// Move r16 to r/m16. 218 pub static MOV_STORE_16: [u8; 2] = [0x66, 0x89]; 219 220 /// Move {r16, r32, r64} to same-sized register or memory. 221 pub static MOV_STORE: [u8; 1] = [0x89]; 222 223 /// Move aligned packed single-precision floating-point values from x/m to xmm (SSE). 224 pub static MOVAPS_LOAD: [u8; 2] = [0x0f, 0x28]; 225 226 /// Move doubleword from r/m32 to xmm (SSE2). Quadword with REX prefix. 227 pub static MOVD_LOAD_XMM: [u8; 3] = [0x66, 0x0f, 0x6e]; 228 229 /// Move doubleword from xmm to r/m32 (SSE2). Quadword with REX prefix. 230 pub static MOVD_STORE_XMM: [u8; 3] = [0x66, 0x0f, 0x7e]; 231 232 /// Move packed single-precision floating-point values low to high (SSE). 233 pub static MOVLHPS: [u8; 2] = [0x0f, 0x16]; 234 235 /// Move scalar double-precision floating-point value (from reg/mem to reg). 236 pub static MOVSD_LOAD: [u8; 3] = [0xf2, 0x0f, 0x10]; 237 238 /// Move scalar double-precision floating-point value (from reg to reg/mem). 239 pub static MOVSD_STORE: [u8; 3] = [0xf2, 0x0f, 0x11]; 240 241 /// Move scalar single-precision floating-point value (from reg to reg/mem). 242 pub static MOVSS_STORE: [u8; 3] = [0xf3, 0x0f, 0x11]; 243 244 /// Move scalar single-precision floating-point-value (from reg/mem to reg). 245 pub static MOVSS_LOAD: [u8; 3] = [0xf3, 0x0f, 0x10]; 246 247 /// Move byte to register with sign-extension. 248 pub static MOVSX_BYTE: [u8; 2] = [0x0f, 0xbe]; 249 250 /// Move word to register with sign-extension. 251 pub static MOVSX_WORD: [u8; 2] = [0x0f, 0xbf]; 252 253 /// Move doubleword to register with sign-extension. 254 pub static MOVSXD: [u8; 1] = [0x63]; 255 256 /// Move unaligned packed single-precision floating-point from x/m to xmm (SSE). 257 pub static MOVUPS_LOAD: [u8; 2] = [0x0f, 0x10]; 258 259 /// Move unaligned packed single-precision floating-point value from xmm to x/m (SSE). 260 pub static MOVUPS_STORE: [u8; 2] = [0x0f, 0x11]; 261 262 /// Move byte to register with zero-extension. 263 pub static MOVZX_BYTE: [u8; 2] = [0x0f, 0xb6]; 264 265 /// Move word to register with zero-extension. 266 pub static MOVZX_WORD: [u8; 2] = [0x0f, 0xb7]; 267 268 /// Unsigned multiply for {16,32,64}-bit. 269 pub static MUL: [u8; 1] = [0xf7]; 270 271 /// Multiply packed double-precision floating-point values from xmm2/mem to xmm1 and store result 272 /// in xmm1 (SSE2). 273 pub static MULPD: [u8; 3] = [0x66, 0x0f, 0x59]; 274 275 /// Multiply packed single-precision floating-point values from xmm2/mem to xmm1 and store result 276 /// in xmm1 (SSE). 277 pub static MULPS: [u8; 2] = [0x0f, 0x59]; 278 279 /// Multiply the low double-precision floating-point value in xmm2/m64 by the 280 /// low double-precision floating-point value in xmm1. 281 pub static MULSD: [u8; 3] = [0xf2, 0x0f, 0x59]; 282 283 /// Multiply the low single-precision floating-point value in xmm2/m32 by the 284 /// low single-precision floating-point value in xmm1. 285 pub static MULSS: [u8; 3] = [0xf3, 0x0f, 0x59]; 286 287 /// Reverse each bit of r/m{16,32,64}. 288 pub static NOT: [u8; 1] = [0xf7]; 289 290 /// r{16,32,64} OR register of same size. 291 pub static OR: [u8; 1] = [0x09]; 292 293 /// imm{16,32} OR r/m{16,32,64}, possibly sign-extended. 294 pub static OR_IMM: [u8; 1] = [0x81]; 295 296 /// r/m{16,32,64} OR sign-extended imm8. 297 pub static OR_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 298 299 /// Return the bitwise logical OR of packed single-precision values in xmm and x/m (SSE). 300 pub static ORPS: [u8; 2] = [0x0f, 0x56]; 301 302 /// Converts 8 packed signed word integers from xmm1 and from xxm2/m128 into 16 packed signed byte 303 /// integers in xmm1 using signed saturation (SSE2). 304 pub static PACKSSWB: [u8; 3] = [0x66, 0x0f, 0x63]; 305 306 /// Converts 4 packed signed doubleword integers from xmm1 and from xmm2/m128 into 8 packed signed 307 /// word integers in xmm1 using signed saturation (SSE2). 308 pub static PACKSSDW: [u8; 3] = [0x66, 0x0f, 0x6b]; 309 310 /// Add packed byte integers from xmm2/m128 and xmm1 (SSE2). 311 pub static PADDB: [u8; 3] = [0x66, 0x0f, 0xfc]; 312 313 /// Add packed doubleword integers from xmm2/m128 and xmm1 (SSE2). 314 pub static PADDD: [u8; 3] = [0x66, 0x0f, 0xfe]; 315 316 /// Add packed quadword integers from xmm2/m128 and xmm1 (SSE2). 317 pub static PADDQ: [u8; 3] = [0x66, 0x0f, 0xd4]; 318 319 /// Add packed word integers from xmm2/m128 and xmm1 (SSE2). 320 pub static PADDW: [u8; 3] = [0x66, 0x0f, 0xfd]; 321 322 /// Add packed signed byte integers from xmm2/m128 and xmm1 saturate the results (SSE). 323 pub static PADDSB: [u8; 3] = [0x66, 0x0f, 0xec]; 324 325 /// Add packed signed word integers from xmm2/m128 and xmm1 saturate the results (SSE). 326 pub static PADDSW: [u8; 3] = [0x66, 0x0f, 0xed]; 327 328 /// Add packed unsigned byte integers from xmm2/m128 and xmm1 saturate the results (SSE). 329 pub static PADDUSB: [u8; 3] = [0x66, 0x0f, 0xdc]; 330 331 /// Add packed unsigned word integers from xmm2/m128 and xmm1 saturate the results (SSE). 332 pub static PADDUSW: [u8; 3] = [0x66, 0x0f, 0xdd]; 333 334 /// Bitwise AND of xmm2/m128 and xmm1 (SSE2). 335 pub static PAND: [u8; 3] = [0x66, 0x0f, 0xdb]; 336 337 /// Bitwise AND NOT of xmm2/m128 and xmm1 (SSE2). 338 pub static PANDN: [u8; 3] = [0x66, 0x0f, 0xdf]; 339 340 /// Average packed unsigned byte integers from xmm2/m128 and xmm1 with rounding (SSE2). 341 pub static PAVGB: [u8; 3] = [0x66, 0x0f, 0xE0]; 342 343 /// Average packed unsigned word integers from xmm2/m128 and xmm1 with rounding (SSE2). 344 pub static PAVGW: [u8; 3] = [0x66, 0x0f, 0xE3]; 345 346 /// Select byte values from xmm1 and xmm2/m128 from mask specified in the high bit of each byte 347 /// in XMM0 and store the values into xmm1 (SSE4.1). 348 pub static PBLENDVB: [u8; 4] = [0x66, 0x0f, 0x38, 0x10]; 349 350 /// Compare packed data for equal (SSE2). 351 pub static PCMPEQB: [u8; 3] = [0x66, 0x0f, 0x74]; 352 353 /// Compare packed data for equal (SSE2). 354 pub static PCMPEQD: [u8; 3] = [0x66, 0x0f, 0x76]; 355 356 /// Compare packed data for equal (SSE4.1). 357 pub static PCMPEQQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x29]; 358 359 /// Compare packed data for equal (SSE2). 360 pub static PCMPEQW: [u8; 3] = [0x66, 0x0f, 0x75]; 361 362 /// Compare packed signed byte integers for greater than (SSE2). 363 pub static PCMPGTB: [u8; 3] = [0x66, 0x0f, 0x64]; 364 365 /// Compare packed signed doubleword integers for greater than (SSE2). 366 pub static PCMPGTD: [u8; 3] = [0x66, 0x0f, 0x66]; 367 368 /// Compare packed signed quadword integers for greater than (SSE4.2). 369 pub static PCMPGTQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x37]; 370 371 /// Compare packed signed word integers for greater than (SSE2). 372 pub static PCMPGTW: [u8; 3] = [0x66, 0x0f, 0x65]; 373 374 /// Extract doubleword or quadword, depending on REX.W (SSE4.1). 375 pub static PEXTR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x16]; 376 377 /// Extract byte (SSE4.1). 378 pub static PEXTRB: [u8; 4] = [0x66, 0x0f, 0x3a, 0x14]; 379 380 /// Extract word (SSE4.1). There is a 3-byte SSE2 variant that can also move to m/16. 381 pub static PEXTRW: [u8; 4] = [0x66, 0x0f, 0x3a, 0x15]; 382 383 /// Insert doubleword or quadword, depending on REX.W (SSE4.1). 384 pub static PINSR: [u8; 4] = [0x66, 0x0f, 0x3a, 0x22]; 385 386 /// Insert byte (SSE4.1). 387 pub static PINSRB: [u8; 4] = [0x66, 0x0f, 0x3a, 0x20]; 388 389 /// Insert word (SSE2). 390 pub static PINSRW: [u8; 3] = [0x66, 0x0f, 0xc4]; 391 392 /// Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed maximum values in 393 /// xmm1 (SSE4.1). 394 pub static PMAXSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x3c]; 395 396 /// Compare packed signed doubleword integers in xmm1 and xmm2/m128 and store packed maximum 397 /// values in xmm1 (SSE4.1). 398 pub static PMAXSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3d]; 399 400 /// Compare packed signed word integers in xmm1 and xmm2/m128 and store packed maximum values in 401 /// xmm1 (SSE2). 402 pub static PMAXSW: [u8; 3] = [0x66, 0x0f, 0xee]; 403 404 /// Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed maximum values in 405 /// xmm1 (SSE2). 406 pub static PMAXUB: [u8; 3] = [0x66, 0x0f, 0xde]; 407 408 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed maximum 409 /// values in xmm1 (SSE4.1). 410 pub static PMAXUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3f]; 411 412 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed maximum values in 413 /// xmm1 (SSE4.1). 414 pub static PMAXUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3e]; 415 416 /// Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed minimum values in 417 /// xmm1 (SSE4.1). 418 pub static PMINSB: [u8; 4] = [0x66, 0x0f, 0x38, 0x38]; 419 420 /// Compare packed signed doubleword integers in xmm1 and xmm2/m128 and store packed minimum 421 /// values in xmm1 (SSE4.1). 422 pub static PMINSD: [u8; 4] = [0x66, 0x0f, 0x38, 0x39]; 423 424 /// Compare packed signed word integers in xmm1 and xmm2/m128 and store packed minimum values in 425 /// xmm1 (SSE2). 426 pub static PMINSW: [u8; 3] = [0x66, 0x0f, 0xea]; 427 428 /// Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed minimum values in 429 /// xmm1 (SSE2). 430 pub static PMINUB: [u8; 3] = [0x66, 0x0f, 0xda]; 431 432 /// Compare packed unsigned doubleword integers in xmm1 and xmm2/m128 and store packed minimum 433 /// values in xmm1 (SSE4.1). 434 pub static PMINUD: [u8; 4] = [0x66, 0x0f, 0x38, 0x3b]; 435 436 /// Compare packed unsigned word integers in xmm1 and xmm2/m128 and store packed minimum values in 437 /// xmm1 (SSE4.1). 438 pub static PMINUW: [u8; 4] = [0x66, 0x0f, 0x38, 0x3a]; 439 440 /// Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit 441 /// integers in xmm1 (SSE4.1). 442 pub static PMOVSXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x20]; 443 444 /// Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit 445 /// integers in xmm1 (SSE4.1). 446 pub static PMOVSXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x23]; 447 448 /// Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit 449 /// integers in xmm1. 450 pub static PMOVSXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x25]; 451 452 /// Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit 453 /// integers in xmm1 (SSE4.1). 454 pub static PMOVZXBW: [u8; 4] = [0x66, 0x0f, 0x38, 0x30]; 455 456 /// Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit 457 /// integers in xmm1 (SSE4.1). 458 pub static PMOVZXWD: [u8; 4] = [0x66, 0x0f, 0x38, 0x33]; 459 460 /// Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit 461 /// integers in xmm1. 462 pub static PMOVZXDQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x35]; 463 464 /// Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of 465 /// the results in xmm1 (SSE2). 466 pub static PMULLW: [u8; 3] = [0x66, 0x0f, 0xd5]; 467 468 /// Multiply the packed doubleword signed integers in xmm1 and xmm2/m128 and store the low 32 469 /// bits of each product in xmm1 (SSE4.1). 470 pub static PMULLD: [u8; 4] = [0x66, 0x0f, 0x38, 0x40]; 471 472 /// Multiply the packed quadword signed integers in xmm2 and xmm3/m128 and store the low 64 473 /// bits of each product in xmm1 (AVX512VL/DQ). Requires an EVEX encoding. 474 pub static VPMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40]; 475 476 /// Multiply packed unsigned doubleword integers in xmm1 by packed unsigned doubleword integers 477 /// in xmm2/m128, and store the quadword results in xmm1 (SSE2). 478 pub static PMULUDQ: [u8; 3] = [0x66, 0x0f, 0xf4]; 479 480 /// Pop top of stack into r{16,32,64}; increment stack pointer. 481 pub static POP_REG: [u8; 1] = [0x58]; 482 483 /// Returns the count of number of bits set to 1. 484 pub static POPCNT: [u8; 3] = [0xf3, 0x0f, 0xb8]; 485 486 /// Bitwise OR of xmm2/m128 and xmm1 (SSE2). 487 pub static POR: [u8; 3] = [0x66, 0x0f, 0xeb]; 488 489 /// Shuffle bytes in xmm1 according to contents of xmm2/m128 (SSE3). 490 pub static PSHUFB: [u8; 4] = [0x66, 0x0f, 0x38, 0x00]; 491 492 /// Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and 493 /// store the result in xmm1 (SSE2). 494 pub static PSHUFD: [u8; 3] = [0x66, 0x0f, 0x70]; 495 496 /// Shift words in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 497 /// digit used in the ModR/M byte (SSE2). 498 pub static PS_W_IMM: [u8; 3] = [0x66, 0x0f, 0x71]; 499 500 /// Shift doublewords in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 501 /// digit used in the ModR/M byte (SSE2). 502 pub static PS_D_IMM: [u8; 3] = [0x66, 0x0f, 0x72]; 503 504 /// Shift quadwords in xmm1 by imm8; the direction and sign-bit behavior is controlled by the RRR 505 /// digit used in the ModR/M byte (SSE2). 506 pub static PS_Q_IMM: [u8; 3] = [0x66, 0x0f, 0x73]; 507 508 /// Shift words in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 509 pub static PSLLW: [u8; 3] = [0x66, 0x0f, 0xf1]; 510 511 /// Shift doublewords in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 512 pub static PSLLD: [u8; 3] = [0x66, 0x0f, 0xf2]; 513 514 /// Shift quadwords in xmm1 left by xmm2/m128 while shifting in 0s (SSE2). 515 pub static PSLLQ: [u8; 3] = [0x66, 0x0f, 0xf3]; 516 517 /// Shift words in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 518 pub static PSRLW: [u8; 3] = [0x66, 0x0f, 0xd1]; 519 520 /// Shift doublewords in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 521 pub static PSRLD: [u8; 3] = [0x66, 0x0f, 0xd2]; 522 523 /// Shift quadwords in xmm1 right by xmm2/m128 while shifting in 0s (SSE2). 524 pub static PSRLQ: [u8; 3] = [0x66, 0x0f, 0xd3]; 525 526 /// Shift words in xmm1 right by xmm2/m128 while shifting in sign bits (SSE2). 527 pub static PSRAW: [u8; 3] = [0x66, 0x0f, 0xe1]; 528 529 /// Shift doublewords in xmm1 right by xmm2/m128 while shifting in sign bits (SSE2). 530 pub static PSRAD: [u8; 3] = [0x66, 0x0f, 0xe2]; 531 532 /// Subtract packed byte integers in xmm2/m128 from packed byte integers in xmm1 (SSE2). 533 pub static PSUBB: [u8; 3] = [0x66, 0x0f, 0xf8]; 534 535 /// Subtract packed word integers in xmm2/m128 from packed word integers in xmm1 (SSE2). 536 pub static PSUBW: [u8; 3] = [0x66, 0x0f, 0xf9]; 537 538 /// Subtract packed doubleword integers in xmm2/m128 from doubleword byte integers in xmm1 (SSE2). 539 pub static PSUBD: [u8; 3] = [0x66, 0x0f, 0xfa]; 540 541 /// Subtract packed quadword integers in xmm2/m128 from xmm1 (SSE2). 542 pub static PSUBQ: [u8; 3] = [0x66, 0x0f, 0xfb]; 543 544 /// Subtract packed signed byte integers in xmm2/m128 from packed signed byte integers in xmm1 545 /// and saturate results (SSE2). 546 pub static PSUBSB: [u8; 3] = [0x66, 0x0f, 0xe8]; 547 548 /// Subtract packed signed word integers in xmm2/m128 from packed signed word integers in xmm1 549 /// and saturate results (SSE2). 550 pub static PSUBSW: [u8; 3] = [0x66, 0x0f, 0xe9]; 551 552 /// Subtract packed unsigned byte integers in xmm2/m128 from packed unsigned byte integers in xmm1 553 /// and saturate results (SSE2). 554 pub static PSUBUSB: [u8; 3] = [0x66, 0x0f, 0xd8]; 555 556 /// Subtract packed unsigned word integers in xmm2/m128 from packed unsigned word integers in xmm1 557 /// and saturate results (SSE2). 558 pub static PSUBUSW: [u8; 3] = [0x66, 0x0f, 0xd9]; 559 560 /// Set ZF if xmm2/m128 AND xmm1 result is all 0s; set CF if xmm2/m128 AND NOT xmm1 result is all 561 /// 0s (SSE4.1). 562 pub static PTEST: [u8; 4] = [0x66, 0x0f, 0x38, 0x17]; 563 564 /// Unpack and interleave high-order bytes from xmm1 and xmm2/m128 into xmm1 (SSE2). 565 pub static PUNPCKHBW: [u8; 3] = [0x66, 0x0f, 0x68]; 566 567 /// Unpack and interleave high-order words from xmm1 and xmm2/m128 into xmm1 (SSE2). 568 pub static PUNPCKHWD: [u8; 3] = [0x66, 0x0f, 0x69]; 569 570 /// Unpack and interleave high-order doublewords from xmm1 and xmm2/m128 into xmm1 (SSE2). 571 pub static PUNPCKHDQ: [u8; 3] = [0x66, 0x0f, 0x6A]; 572 573 /// Unpack and interleave high-order quadwords from xmm1 and xmm2/m128 into xmm1 (SSE2). 574 pub static PUNPCKHQDQ: [u8; 3] = [0x66, 0x0f, 0x6D]; 575 576 /// Unpack and interleave low-order bytes from xmm1 and xmm2/m128 into xmm1 (SSE2). 577 pub static PUNPCKLBW: [u8; 3] = [0x66, 0x0f, 0x60]; 578 579 /// Unpack and interleave low-order words from xmm1 and xmm2/m128 into xmm1 (SSE2). 580 pub static PUNPCKLWD: [u8; 3] = [0x66, 0x0f, 0x61]; 581 582 /// Unpack and interleave low-order doublewords from xmm1 and xmm2/m128 into xmm1 (SSE2). 583 pub static PUNPCKLDQ: [u8; 3] = [0x66, 0x0f, 0x62]; 584 585 /// Unpack and interleave low-order quadwords from xmm1 and xmm2/m128 into xmm1 (SSE2). 586 pub static PUNPCKLQDQ: [u8; 3] = [0x66, 0x0f, 0x6C]; 587 588 /// Push r{16,32,64}. 589 pub static PUSH_REG: [u8; 1] = [0x50]; 590 591 /// Logical exclusive OR (SSE2). 592 pub static PXOR: [u8; 3] = [0x66, 0x0f, 0xef]; 593 594 /// Near return to calling procedure. 595 pub static RET_NEAR: [u8; 1] = [0xc3]; 596 597 /// General rotation opcode. Kind of rotation depends on encoding. 598 pub static ROTATE_CL: [u8; 1] = [0xd3]; 599 600 /// General rotation opcode. Kind of rotation depends on encoding. 601 pub static ROTATE_IMM8: [u8; 1] = [0xc1]; 602 603 /// Round scalar doubl-precision floating-point values. 604 pub static ROUNDSD: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0b]; 605 606 /// Round scalar single-precision floating-point values. 607 pub static ROUNDSS: [u8; 4] = [0x66, 0x0f, 0x3a, 0x0a]; 608 609 /// Subtract with borrow r{16,32,64} from r/m of the same size. 610 pub static SBB: [u8; 1] = [0x19]; 611 612 /// Set byte if overflow (OF=1). 613 pub static SET_BYTE_IF_OVERFLOW: [u8; 2] = [0x0f, 0x90]; 614 615 /// Compute the square root of the packed double-precision floating-point values and store the 616 /// result in xmm1 (SSE2). 617 pub static SQRTPD: [u8; 3] = [0x66, 0x0f, 0x51]; 618 619 /// Compute the square root of the packed double-precision floating-point values and store the 620 /// result in xmm1 (SSE). 621 pub static SQRTPS: [u8; 2] = [0x0f, 0x51]; 622 623 /// Compute square root of scalar double-precision floating-point value. 624 pub static SQRTSD: [u8; 3] = [0xf2, 0x0f, 0x51]; 625 626 /// Compute square root of scalar single-precision value. 627 pub static SQRTSS: [u8; 3] = [0xf3, 0x0f, 0x51]; 628 629 /// Subtract r{16,32,64} from r/m of same size. 630 pub static SUB: [u8; 1] = [0x29]; 631 632 /// Subtract packed double-precision floating-point values in xmm2/mem from xmm1 and store result 633 /// in xmm1 (SSE2). 634 pub static SUBPD: [u8; 3] = [0x66, 0x0f, 0x5c]; 635 636 /// Subtract packed single-precision floating-point values in xmm2/mem from xmm1 and store result 637 /// in xmm1 (SSE). 638 pub static SUBPS: [u8; 2] = [0x0f, 0x5c]; 639 640 /// Subtract the low double-precision floating-point value in xmm2/m64 from xmm1 641 /// and store the result in xmm1. 642 pub static SUBSD: [u8; 3] = [0xf2, 0x0f, 0x5c]; 643 644 /// Subtract the low single-precision floating-point value in xmm2/m32 from xmm1 645 /// and store the result in xmm1. 646 pub static SUBSS: [u8; 3] = [0xf3, 0x0f, 0x5c]; 647 648 /// AND r8 with r/m8; set SF, ZF, PF according to result. 649 pub static TEST_BYTE_REG: [u8; 1] = [0x84]; 650 651 /// AND {r16, r32, r64} with r/m of the same size; set SF, ZF, PF according to result. 652 pub static TEST_REG: [u8; 1] = [0x85]; 653 654 /// Count the number of trailing zero bits. 655 pub static TZCNT: [u8; 3] = [0xf3, 0x0f, 0xbc]; 656 657 /// Compare low double-precision floating-point values in xmm1 and xmm2/mem64 658 /// and set the EFLAGS flags accordingly. 659 pub static UCOMISD: [u8; 3] = [0x66, 0x0f, 0x2e]; 660 661 /// Compare low single-precision floating-point values in xmm1 and xmm2/mem32 662 /// and set the EFLAGS flags accordingly. 663 pub static UCOMISS: [u8; 2] = [0x0f, 0x2e]; 664 665 /// Raise invalid opcode instruction. 666 pub static UNDEFINED2: [u8; 2] = [0x0f, 0x0b]; 667 668 /// imm{16,32} XOR r/m{16,32,64}, possibly sign-extended. 669 pub static XOR_IMM: [u8; 1] = [0x81]; 670 671 /// r/m{16,32,64} XOR sign-extended imm8. 672 pub static XOR_IMM8_SIGN_EXTEND: [u8; 1] = [0x83]; 673 674 /// r/m{16,32,64} XOR register of the same size. 675 pub static XOR: [u8; 1] = [0x31]; 676 677 /// r/m8 XOR r8. 678 pub static XORB: [u8; 1] = [0x30]; 679 680 /// Bitwise logical XOR of packed double-precision floating-point values. 681 pub static XORPD: [u8; 3] = [0x66, 0x0f, 0x57]; 682 683 /// Bitwise logical XOR of packed single-precision floating-point values. 684 pub static XORPS: [u8; 2] = [0x0f, 0x57]; 685