1 // REQUIRES: aarch64-registered-target
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - %s >/dev/null 2>%t
4 // RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
5
6 // If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README for instructions on how to resolve it.
7 // ASM-NOT: warning
8 #include <arm_sve.h>
9
test_svldnf1sh_s32(svbool_t pg,const int16_t * base)10 svint32_t test_svldnf1sh_s32(svbool_t pg, const int16_t *base)
11 {
12 // CHECK-LABEL: test_svldnf1sh_s32
13 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
14 // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %base)
15 // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
16 // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
17 return svldnf1sh_s32(pg, base);
18 }
19
test_svldnf1sh_s64(svbool_t pg,const int16_t * base)20 svint64_t test_svldnf1sh_s64(svbool_t pg, const int16_t *base)
21 {
22 // CHECK-LABEL: test_svldnf1sh_s64
23 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
24 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %base)
25 // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
26 // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
27 return svldnf1sh_s64(pg, base);
28 }
29
test_svldnf1sh_u32(svbool_t pg,const int16_t * base)30 svuint32_t test_svldnf1sh_u32(svbool_t pg, const int16_t *base)
31 {
32 // CHECK-LABEL: test_svldnf1sh_u32
33 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
34 // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %base)
35 // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
36 // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
37 return svldnf1sh_u32(pg, base);
38 }
39
test_svldnf1sh_u64(svbool_t pg,const int16_t * base)40 svuint64_t test_svldnf1sh_u64(svbool_t pg, const int16_t *base)
41 {
42 // CHECK-LABEL: test_svldnf1sh_u64
43 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
44 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %base)
45 // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
46 // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
47 return svldnf1sh_u64(pg, base);
48 }
49
test_svldnf1sh_vnum_s32(svbool_t pg,const int16_t * base,int64_t vnum)50 svint32_t test_svldnf1sh_vnum_s32(svbool_t pg, const int16_t *base, int64_t vnum)
51 {
52 // CHECK-LABEL: test_svldnf1sh_vnum_s32
53 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
54 // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
55 // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BITCAST]], i64 %vnum, i64 0
56 // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
57 // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
58 // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
59 return svldnf1sh_vnum_s32(pg, base, vnum);
60 }
61
test_svldnf1sh_vnum_s64(svbool_t pg,const int16_t * base,int64_t vnum)62 svint64_t test_svldnf1sh_vnum_s64(svbool_t pg, const int16_t *base, int64_t vnum)
63 {
64 // CHECK-LABEL: test_svldnf1sh_vnum_s64
65 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
66 // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
67 // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BITCAST]], i64 %vnum, i64 0
68 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
69 // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
70 // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
71 return svldnf1sh_vnum_s64(pg, base, vnum);
72 }
73
test_svldnf1sh_vnum_u32(svbool_t pg,const int16_t * base,int64_t vnum)74 svuint32_t test_svldnf1sh_vnum_u32(svbool_t pg, const int16_t *base, int64_t vnum)
75 {
76 // CHECK-LABEL: test_svldnf1sh_vnum_u32
77 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
78 // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
79 // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BITCAST]], i64 %vnum, i64 0
80 // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ldnf1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
81 // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
82 // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
83 return svldnf1sh_vnum_u32(pg, base, vnum);
84 }
85
test_svldnf1sh_vnum_u64(svbool_t pg,const int16_t * base,int64_t vnum)86 svuint64_t test_svldnf1sh_vnum_u64(svbool_t pg, const int16_t *base, int64_t vnum)
87 {
88 // CHECK-LABEL: test_svldnf1sh_vnum_u64
89 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
90 // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
91 // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BITCAST]], i64 %vnum, i64 0
92 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ldnf1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
93 // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
94 // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
95 return svldnf1sh_vnum_u64(pg, base, vnum);
96 }
97