1 // REQUIRES: aarch64-registered-target
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - %s >/dev/null 2>%t
4 // RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
5
6 // If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README for instructions on how to resolve it.
7 // ASM-NOT: warning
8 #include <arm_sve.h>
9
test_svldnf1uw_s64(svbool_t pg,const uint32_t * base)10 svint64_t test_svldnf1uw_s64(svbool_t pg, const uint32_t *base)
11 {
12 // CHECK-LABEL: test_svldnf1uw_s64
13 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
14 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %base)
15 // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
16 // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
17 return svldnf1uw_s64(pg, base);
18 }
19
test_svldnf1uw_u64(svbool_t pg,const uint32_t * base)20 svuint64_t test_svldnf1uw_u64(svbool_t pg, const uint32_t *base)
21 {
22 // CHECK-LABEL: test_svldnf1uw_u64
23 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
24 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %base)
25 // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
26 // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
27 return svldnf1uw_u64(pg, base);
28 }
29
test_svldnf1uw_vnum_s64(svbool_t pg,const uint32_t * base,int64_t vnum)30 svint64_t test_svldnf1uw_vnum_s64(svbool_t pg, const uint32_t *base, int64_t vnum)
31 {
32 // CHECK-LABEL: test_svldnf1uw_vnum_s64
33 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
34 // CHECK-DAG: %[[BITCAST:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
35 // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BITCAST]], i64 %vnum, i64 0
36 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
37 // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
38 // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
39 return svldnf1uw_vnum_s64(pg, base, vnum);
40 }
41
test_svldnf1uw_vnum_u64(svbool_t pg,const uint32_t * base,int64_t vnum)42 svuint64_t test_svldnf1uw_vnum_u64(svbool_t pg, const uint32_t *base, int64_t vnum)
43 {
44 // CHECK-LABEL: test_svldnf1uw_vnum_u64
45 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
46 // CHECK-DAG: %[[BITCAST:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
47 // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BITCAST]], i64 %vnum, i64 0
48 // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ldnf1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
49 // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
50 // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
51 return svldnf1uw_vnum_u64(pg, base, vnum);
52 }
53