1 // REQUIRES: aarch64-registered-target
2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
3 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
4 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o - %s >/dev/null 2>%t
5 // RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
6
7 // If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README for instructions on how to resolve it.
8 // ASM-NOT: warning
9 #include <arm_sve.h>
10
11 #ifdef SVE_OVERLOADED_FORMS
12 // A simple used,unused... macro, long enough to represent any SVE builtin.
13 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
14 #else
15 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
16 #endif
17
test_svmad_s8_z(svbool_t pg,svint8_t op1,svint8_t op2,svint8_t op3)18 svint8_t test_svmad_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3)
19 {
20 // CHECK-LABEL: test_svmad_s8_z
21 // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
22 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3)
23 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
24 return SVE_ACLE_FUNC(svmad,_s8,_z,)(pg, op1, op2, op3);
25 }
26
test_svmad_s16_z(svbool_t pg,svint16_t op1,svint16_t op2,svint16_t op3)27 svint16_t test_svmad_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t op3)
28 {
29 // CHECK-LABEL: test_svmad_s16_z
30 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
31 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
32 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3)
33 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
34 return SVE_ACLE_FUNC(svmad,_s16,_z,)(pg, op1, op2, op3);
35 }
36
test_svmad_s32_z(svbool_t pg,svint32_t op1,svint32_t op2,svint32_t op3)37 svint32_t test_svmad_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t op3)
38 {
39 // CHECK-LABEL: test_svmad_s32_z
40 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
41 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
42 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3)
43 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
44 return SVE_ACLE_FUNC(svmad,_s32,_z,)(pg, op1, op2, op3);
45 }
46
test_svmad_s64_z(svbool_t pg,svint64_t op1,svint64_t op2,svint64_t op3)47 svint64_t test_svmad_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t op3)
48 {
49 // CHECK-LABEL: test_svmad_s64_z
50 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
51 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
52 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3)
53 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
54 return SVE_ACLE_FUNC(svmad,_s64,_z,)(pg, op1, op2, op3);
55 }
56
test_svmad_u8_z(svbool_t pg,svuint8_t op1,svuint8_t op2,svuint8_t op3)57 svuint8_t test_svmad_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t op3)
58 {
59 // CHECK-LABEL: test_svmad_u8_z
60 // CHECK: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
61 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3)
62 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
63 return SVE_ACLE_FUNC(svmad,_u8,_z,)(pg, op1, op2, op3);
64 }
65
test_svmad_u16_z(svbool_t pg,svuint16_t op1,svuint16_t op2,svuint16_t op3)66 svuint16_t test_svmad_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint16_t op3)
67 {
68 // CHECK-LABEL: test_svmad_u16_z
69 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
70 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
71 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3)
72 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
73 return SVE_ACLE_FUNC(svmad,_u16,_z,)(pg, op1, op2, op3);
74 }
75
test_svmad_u32_z(svbool_t pg,svuint32_t op1,svuint32_t op2,svuint32_t op3)76 svuint32_t test_svmad_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint32_t op3)
77 {
78 // CHECK-LABEL: test_svmad_u32_z
79 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
80 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sel.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> zeroinitializer)
81 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3)
82 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
83 return SVE_ACLE_FUNC(svmad,_u32,_z,)(pg, op1, op2, op3);
84 }
85
test_svmad_u64_z(svbool_t pg,svuint64_t op1,svuint64_t op2,svuint64_t op3)86 svuint64_t test_svmad_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint64_t op3)
87 {
88 // CHECK-LABEL: test_svmad_u64_z
89 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
90 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
91 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3)
92 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
93 return SVE_ACLE_FUNC(svmad,_u64,_z,)(pg, op1, op2, op3);
94 }
95
test_svmad_s8_m(svbool_t pg,svint8_t op1,svint8_t op2,svint8_t op3)96 svint8_t test_svmad_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3)
97 {
98 // CHECK-LABEL: test_svmad_s8_m
99 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3)
100 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
101 return SVE_ACLE_FUNC(svmad,_s8,_m,)(pg, op1, op2, op3);
102 }
103
test_svmad_s16_m(svbool_t pg,svint16_t op1,svint16_t op2,svint16_t op3)104 svint16_t test_svmad_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t op3)
105 {
106 // CHECK-LABEL: test_svmad_s16_m
107 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
108 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3)
109 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
110 return SVE_ACLE_FUNC(svmad,_s16,_m,)(pg, op1, op2, op3);
111 }
112
test_svmad_s32_m(svbool_t pg,svint32_t op1,svint32_t op2,svint32_t op3)113 svint32_t test_svmad_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t op3)
114 {
115 // CHECK-LABEL: test_svmad_s32_m
116 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
117 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3)
118 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
119 return SVE_ACLE_FUNC(svmad,_s32,_m,)(pg, op1, op2, op3);
120 }
121
test_svmad_s64_m(svbool_t pg,svint64_t op1,svint64_t op2,svint64_t op3)122 svint64_t test_svmad_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t op3)
123 {
124 // CHECK-LABEL: test_svmad_s64_m
125 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
126 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3)
127 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
128 return SVE_ACLE_FUNC(svmad,_s64,_m,)(pg, op1, op2, op3);
129 }
130
test_svmad_u8_m(svbool_t pg,svuint8_t op1,svuint8_t op2,svuint8_t op3)131 svuint8_t test_svmad_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t op3)
132 {
133 // CHECK-LABEL: test_svmad_u8_m
134 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3)
135 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
136 return SVE_ACLE_FUNC(svmad,_u8,_m,)(pg, op1, op2, op3);
137 }
138
test_svmad_u16_m(svbool_t pg,svuint16_t op1,svuint16_t op2,svuint16_t op3)139 svuint16_t test_svmad_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint16_t op3)
140 {
141 // CHECK-LABEL: test_svmad_u16_m
142 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
143 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3)
144 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
145 return SVE_ACLE_FUNC(svmad,_u16,_m,)(pg, op1, op2, op3);
146 }
147
test_svmad_u32_m(svbool_t pg,svuint32_t op1,svuint32_t op2,svuint32_t op3)148 svuint32_t test_svmad_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint32_t op3)
149 {
150 // CHECK-LABEL: test_svmad_u32_m
151 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
152 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3)
153 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
154 return SVE_ACLE_FUNC(svmad,_u32,_m,)(pg, op1, op2, op3);
155 }
156
test_svmad_u64_m(svbool_t pg,svuint64_t op1,svuint64_t op2,svuint64_t op3)157 svuint64_t test_svmad_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint64_t op3)
158 {
159 // CHECK-LABEL: test_svmad_u64_m
160 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
161 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3)
162 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
163 return SVE_ACLE_FUNC(svmad,_u64,_m,)(pg, op1, op2, op3);
164 }
165
test_svmad_s8_x(svbool_t pg,svint8_t op1,svint8_t op2,svint8_t op3)166 svint8_t test_svmad_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, svint8_t op3)
167 {
168 // CHECK-LABEL: test_svmad_s8_x
169 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3)
170 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
171 return SVE_ACLE_FUNC(svmad,_s8,_x,)(pg, op1, op2, op3);
172 }
173
test_svmad_s16_x(svbool_t pg,svint16_t op1,svint16_t op2,svint16_t op3)174 svint16_t test_svmad_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, svint16_t op3)
175 {
176 // CHECK-LABEL: test_svmad_s16_x
177 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
178 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3)
179 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
180 return SVE_ACLE_FUNC(svmad,_s16,_x,)(pg, op1, op2, op3);
181 }
182
test_svmad_s32_x(svbool_t pg,svint32_t op1,svint32_t op2,svint32_t op3)183 svint32_t test_svmad_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, svint32_t op3)
184 {
185 // CHECK-LABEL: test_svmad_s32_x
186 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
187 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3)
188 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
189 return SVE_ACLE_FUNC(svmad,_s32,_x,)(pg, op1, op2, op3);
190 }
191
test_svmad_s64_x(svbool_t pg,svint64_t op1,svint64_t op2,svint64_t op3)192 svint64_t test_svmad_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, svint64_t op3)
193 {
194 // CHECK-LABEL: test_svmad_s64_x
195 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
196 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3)
197 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
198 return SVE_ACLE_FUNC(svmad,_s64,_x,)(pg, op1, op2, op3);
199 }
200
test_svmad_u8_x(svbool_t pg,svuint8_t op1,svuint8_t op2,svuint8_t op3)201 svuint8_t test_svmad_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, svuint8_t op3)
202 {
203 // CHECK-LABEL: test_svmad_u8_x
204 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %op3)
205 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
206 return SVE_ACLE_FUNC(svmad,_u8,_x,)(pg, op1, op2, op3);
207 }
208
test_svmad_u16_x(svbool_t pg,svuint16_t op1,svuint16_t op2,svuint16_t op3)209 svuint16_t test_svmad_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, svuint16_t op3)
210 {
211 // CHECK-LABEL: test_svmad_u16_x
212 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
213 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %op3)
214 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
215 return SVE_ACLE_FUNC(svmad,_u16,_x,)(pg, op1, op2, op3);
216 }
217
test_svmad_u32_x(svbool_t pg,svuint32_t op1,svuint32_t op2,svuint32_t op3)218 svuint32_t test_svmad_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, svuint32_t op3)
219 {
220 // CHECK-LABEL: test_svmad_u32_x
221 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
222 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %op3)
223 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
224 return SVE_ACLE_FUNC(svmad,_u32,_x,)(pg, op1, op2, op3);
225 }
226
test_svmad_u64_x(svbool_t pg,svuint64_t op1,svuint64_t op2,svuint64_t op3)227 svuint64_t test_svmad_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, svuint64_t op3)
228 {
229 // CHECK-LABEL: test_svmad_u64_x
230 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
231 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %op3)
232 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
233 return SVE_ACLE_FUNC(svmad,_u64,_x,)(pg, op1, op2, op3);
234 }
235
test_svmad_n_s8_z(svbool_t pg,svint8_t op1,svint8_t op2,int8_t op3)236 svint8_t test_svmad_n_s8_z(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3)
237 {
238 // CHECK-LABEL: test_svmad_n_s8_z
239 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op3)
240 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
241 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2, <vscale x 16 x i8> %[[DUP]])
242 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
243 return SVE_ACLE_FUNC(svmad,_n_s8,_z,)(pg, op1, op2, op3);
244 }
245
test_svmad_n_s16_z(svbool_t pg,svint16_t op1,svint16_t op2,int16_t op3)246 svint16_t test_svmad_n_s16_z(svbool_t pg, svint16_t op1, svint16_t op2, int16_t op3)
247 {
248 // CHECK-LABEL: test_svmad_n_s16_z
249 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
250 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op3)
251 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
252 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2, <vscale x 8 x i16> %[[DUP]])
253 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
254 return SVE_ACLE_FUNC(svmad,_n_s16,_z,)(pg, op1, op2, op3);
255 }
256
test_svmad_n_s32_z(svbool_t pg,svint32_t op1,svint32_t op2,int32_t op3)257 svint32_t test_svmad_n_s32_z(svbool_t pg, svint32_t op1, svint32_t op2, int32_t op3)
258 {
259 // CHECK-LABEL: test_svmad_n_s32_z
260 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
261 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op3)
262 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2, <vscale x 4 x i32> %[[DUP]])
263 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
264 return SVE_ACLE_FUNC(svmad,_n_s32,_z,)(pg, op1, op2, op3);
265 }
266
test_svmad_n_s64_z(svbool_t pg,svint64_t op1,svint64_t op2,int64_t op3)267 svint64_t test_svmad_n_s64_z(svbool_t pg, svint64_t op1, svint64_t op2, int64_t op3)
268 {
269 // CHECK-LABEL: test_svmad_n_s64_z
270 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
271 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op3)
272 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
273 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2, <vscale x 2 x i64> %[[DUP]])
274 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
275 return SVE_ACLE_FUNC(svmad,_n_s64,_z,)(pg, op1, op2, op3);
276 }
277
test_svmad_n_u8_z(svbool_t pg,svuint8_t op1,svuint8_t op2,uint8_t op3)278 svuint8_t test_svmad_n_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t op3)
279 {
280 // CHECK-LABEL: test_svmad_n_u8_z
281 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op3)
282 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.sel.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> zeroinitializer)
283 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %[[SEL]], <vscale x 16 x i8> %op2, <vscale x 16 x i8> %[[DUP]])
284 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
285 return SVE_ACLE_FUNC(svmad,_n_u8,_z,)(pg, op1, op2, op3);
286 }
287
test_svmad_n_u16_z(svbool_t pg,svuint16_t op1,svuint16_t op2,uint16_t op3)288 svuint16_t test_svmad_n_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2, uint16_t op3)
289 {
290 // CHECK-LABEL: test_svmad_n_u16_z
291 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
292 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op3)
293 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sel.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> zeroinitializer)
294 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %[[SEL]], <vscale x 8 x i16> %op2, <vscale x 8 x i16> %[[DUP]])
295 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
296 return SVE_ACLE_FUNC(svmad,_n_u16,_z,)(pg, op1, op2, op3);
297 }
298
test_svmad_n_u32_z(svbool_t pg,svuint32_t op1,svuint32_t op2,uint32_t op3)299 svuint32_t test_svmad_n_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2, uint32_t op3)
300 {
301 // CHECK-LABEL: test_svmad_n_u32_z
302 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
303 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op3)
304 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %[[SEL]], <vscale x 4 x i32> %op2, <vscale x 4 x i32> %[[DUP]])
305 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
306 return SVE_ACLE_FUNC(svmad,_n_u32,_z,)(pg, op1, op2, op3);
307 }
308
test_svmad_n_u64_z(svbool_t pg,svuint64_t op1,svuint64_t op2,uint64_t op3)309 svuint64_t test_svmad_n_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2, uint64_t op3)
310 {
311 // CHECK-LABEL: test_svmad_n_u64_z
312 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
313 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op3)
314 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sel.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> zeroinitializer)
315 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %[[SEL]], <vscale x 2 x i64> %op2, <vscale x 2 x i64> %[[DUP]])
316 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
317 return SVE_ACLE_FUNC(svmad,_n_u64,_z,)(pg, op1, op2, op3);
318 }
319
test_svmad_n_s8_m(svbool_t pg,svint8_t op1,svint8_t op2,int8_t op3)320 svint8_t test_svmad_n_s8_m(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3)
321 {
322 // CHECK-LABEL: test_svmad_n_s8_m
323 // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op3)
324 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %[[DUP]])
325 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
326 return SVE_ACLE_FUNC(svmad,_n_s8,_m,)(pg, op1, op2, op3);
327 }
328
test_svmad_n_s16_m(svbool_t pg,svint16_t op1,svint16_t op2,int16_t op3)329 svint16_t test_svmad_n_s16_m(svbool_t pg, svint16_t op1, svint16_t op2, int16_t op3)
330 {
331 // CHECK-LABEL: test_svmad_n_s16_m
332 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
333 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op3)
334 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %[[DUP]])
335 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
336 return SVE_ACLE_FUNC(svmad,_n_s16,_m,)(pg, op1, op2, op3);
337 }
338
test_svmad_n_s32_m(svbool_t pg,svint32_t op1,svint32_t op2,int32_t op3)339 svint32_t test_svmad_n_s32_m(svbool_t pg, svint32_t op1, svint32_t op2, int32_t op3)
340 {
341 // CHECK-LABEL: test_svmad_n_s32_m
342 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
343 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op3)
344 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %[[DUP]])
345 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
346 return SVE_ACLE_FUNC(svmad,_n_s32,_m,)(pg, op1, op2, op3);
347 }
348
test_svmad_n_s64_m(svbool_t pg,svint64_t op1,svint64_t op2,int64_t op3)349 svint64_t test_svmad_n_s64_m(svbool_t pg, svint64_t op1, svint64_t op2, int64_t op3)
350 {
351 // CHECK-LABEL: test_svmad_n_s64_m
352 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
353 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op3)
354 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %[[DUP]])
355 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
356 return SVE_ACLE_FUNC(svmad,_n_s64,_m,)(pg, op1, op2, op3);
357 }
358
test_svmad_n_u8_m(svbool_t pg,svuint8_t op1,svuint8_t op2,uint8_t op3)359 svuint8_t test_svmad_n_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t op3)
360 {
361 // CHECK-LABEL: test_svmad_n_u8_m
362 // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op3)
363 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %[[DUP]])
364 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
365 return SVE_ACLE_FUNC(svmad,_n_u8,_m,)(pg, op1, op2, op3);
366 }
367
test_svmad_n_u16_m(svbool_t pg,svuint16_t op1,svuint16_t op2,uint16_t op3)368 svuint16_t test_svmad_n_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2, uint16_t op3)
369 {
370 // CHECK-LABEL: test_svmad_n_u16_m
371 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
372 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op3)
373 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %[[DUP]])
374 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
375 return SVE_ACLE_FUNC(svmad,_n_u16,_m,)(pg, op1, op2, op3);
376 }
377
test_svmad_n_u32_m(svbool_t pg,svuint32_t op1,svuint32_t op2,uint32_t op3)378 svuint32_t test_svmad_n_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2, uint32_t op3)
379 {
380 // CHECK-LABEL: test_svmad_n_u32_m
381 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
382 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op3)
383 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %[[DUP]])
384 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
385 return SVE_ACLE_FUNC(svmad,_n_u32,_m,)(pg, op1, op2, op3);
386 }
387
test_svmad_n_u64_m(svbool_t pg,svuint64_t op1,svuint64_t op2,uint64_t op3)388 svuint64_t test_svmad_n_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2, uint64_t op3)
389 {
390 // CHECK-LABEL: test_svmad_n_u64_m
391 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
392 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op3)
393 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %[[DUP]])
394 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
395 return SVE_ACLE_FUNC(svmad,_n_u64,_m,)(pg, op1, op2, op3);
396 }
397
test_svmad_n_s8_x(svbool_t pg,svint8_t op1,svint8_t op2,int8_t op3)398 svint8_t test_svmad_n_s8_x(svbool_t pg, svint8_t op1, svint8_t op2, int8_t op3)
399 {
400 // CHECK-LABEL: test_svmad_n_s8_x
401 // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op3)
402 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %[[DUP]])
403 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
404 return SVE_ACLE_FUNC(svmad,_n_s8,_x,)(pg, op1, op2, op3);
405 }
406
test_svmad_n_s16_x(svbool_t pg,svint16_t op1,svint16_t op2,int16_t op3)407 svint16_t test_svmad_n_s16_x(svbool_t pg, svint16_t op1, svint16_t op2, int16_t op3)
408 {
409 // CHECK-LABEL: test_svmad_n_s16_x
410 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
411 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op3)
412 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %[[DUP]])
413 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
414 return SVE_ACLE_FUNC(svmad,_n_s16,_x,)(pg, op1, op2, op3);
415 }
416
test_svmad_n_s32_x(svbool_t pg,svint32_t op1,svint32_t op2,int32_t op3)417 svint32_t test_svmad_n_s32_x(svbool_t pg, svint32_t op1, svint32_t op2, int32_t op3)
418 {
419 // CHECK-LABEL: test_svmad_n_s32_x
420 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
421 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op3)
422 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %[[DUP]])
423 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
424 return SVE_ACLE_FUNC(svmad,_n_s32,_x,)(pg, op1, op2, op3);
425 }
426
test_svmad_n_s64_x(svbool_t pg,svint64_t op1,svint64_t op2,int64_t op3)427 svint64_t test_svmad_n_s64_x(svbool_t pg, svint64_t op1, svint64_t op2, int64_t op3)
428 {
429 // CHECK-LABEL: test_svmad_n_s64_x
430 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
431 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op3)
432 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %[[DUP]])
433 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
434 return SVE_ACLE_FUNC(svmad,_n_s64,_x,)(pg, op1, op2, op3);
435 }
436
test_svmad_n_u8_x(svbool_t pg,svuint8_t op1,svuint8_t op2,uint8_t op3)437 svuint8_t test_svmad_n_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2, uint8_t op3)
438 {
439 // CHECK-LABEL: test_svmad_n_u8_x
440 // CHECK: %[[DUP:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.x.nxv16i8(i8 %op3)
441 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %op2, <vscale x 16 x i8> %[[DUP]])
442 // CHECK: ret <vscale x 16 x i8> %[[INTRINSIC]]
443 return SVE_ACLE_FUNC(svmad,_n_u8,_x,)(pg, op1, op2, op3);
444 }
445
test_svmad_n_u16_x(svbool_t pg,svuint16_t op1,svuint16_t op2,uint16_t op3)446 svuint16_t test_svmad_n_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2, uint16_t op3)
447 {
448 // CHECK-LABEL: test_svmad_n_u16_x
449 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
450 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.x.nxv8i16(i16 %op3)
451 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.mad.nxv8i16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> %op1, <vscale x 8 x i16> %op2, <vscale x 8 x i16> %[[DUP]])
452 // CHECK: ret <vscale x 8 x i16> %[[INTRINSIC]]
453 return SVE_ACLE_FUNC(svmad,_n_u16,_x,)(pg, op1, op2, op3);
454 }
455
test_svmad_n_u32_x(svbool_t pg,svuint32_t op1,svuint32_t op2,uint32_t op3)456 svuint32_t test_svmad_n_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2, uint32_t op3)
457 {
458 // CHECK-LABEL: test_svmad_n_u32_x
459 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
460 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 %op3)
461 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %op1, <vscale x 4 x i32> %op2, <vscale x 4 x i32> %[[DUP]])
462 // CHECK: ret <vscale x 4 x i32> %[[INTRINSIC]]
463 return SVE_ACLE_FUNC(svmad,_n_u32,_x,)(pg, op1, op2, op3);
464 }
465
test_svmad_n_u64_x(svbool_t pg,svuint64_t op1,svuint64_t op2,uint64_t op3)466 svuint64_t test_svmad_n_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2, uint64_t op3)
467 {
468 // CHECK-LABEL: test_svmad_n_u64_x
469 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
470 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.x.nxv2i64(i64 %op3)
471 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.mad.nxv2i64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> %op1, <vscale x 2 x i64> %op2, <vscale x 2 x i64> %[[DUP]])
472 // CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
473 return SVE_ACLE_FUNC(svmad,_n_u64,_x,)(pg, op1, op2, op3);
474 }
475
test_svmad_f16_z(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)476 svfloat16_t test_svmad_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
477 {
478 // CHECK-LABEL: test_svmad_f16_z
479 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
480 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
481 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
482 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
483 return SVE_ACLE_FUNC(svmad,_f16,_z,)(pg, op1, op2, op3);
484 }
485
test_svmad_f32_z(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)486 svfloat32_t test_svmad_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
487 {
488 // CHECK-LABEL: test_svmad_f32_z
489 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
490 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
491 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
492 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
493 return SVE_ACLE_FUNC(svmad,_f32,_z,)(pg, op1, op2, op3);
494 }
495
test_svmad_f64_z(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)496 svfloat64_t test_svmad_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
497 {
498 // CHECK-LABEL: test_svmad_f64_z
499 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
500 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
501 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
502 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
503 return SVE_ACLE_FUNC(svmad,_f64,_z,)(pg, op1, op2, op3);
504 }
505
test_svmad_f16_m(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)506 svfloat16_t test_svmad_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
507 {
508 // CHECK-LABEL: test_svmad_f16_m
509 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
510 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
511 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
512 return SVE_ACLE_FUNC(svmad,_f16,_m,)(pg, op1, op2, op3);
513 }
514
test_svmad_f32_m(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)515 svfloat32_t test_svmad_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
516 {
517 // CHECK-LABEL: test_svmad_f32_m
518 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
519 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
520 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
521 return SVE_ACLE_FUNC(svmad,_f32,_m,)(pg, op1, op2, op3);
522 }
523
test_svmad_f64_m(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)524 svfloat64_t test_svmad_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
525 {
526 // CHECK-LABEL: test_svmad_f64_m
527 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
528 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
529 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
530 return SVE_ACLE_FUNC(svmad,_f64,_m,)(pg, op1, op2, op3);
531 }
532
test_svmad_f16_x(svbool_t pg,svfloat16_t op1,svfloat16_t op2,svfloat16_t op3)533 svfloat16_t test_svmad_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
534 {
535 // CHECK-LABEL: test_svmad_f16_x
536 // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
537 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %op3)
538 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
539 return SVE_ACLE_FUNC(svmad,_f16,_x,)(pg, op1, op2, op3);
540 }
541
test_svmad_f32_x(svbool_t pg,svfloat32_t op1,svfloat32_t op2,svfloat32_t op3)542 svfloat32_t test_svmad_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
543 {
544 // CHECK-LABEL: test_svmad_f32_x
545 // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
546 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %op3)
547 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
548 return SVE_ACLE_FUNC(svmad,_f32,_x,)(pg, op1, op2, op3);
549 }
550
test_svmad_f64_x(svbool_t pg,svfloat64_t op1,svfloat64_t op2,svfloat64_t op3)551 svfloat64_t test_svmad_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
552 {
553 // CHECK-LABEL: test_svmad_f64_x
554 // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
555 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %op3)
556 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
557 return SVE_ACLE_FUNC(svmad,_f64,_x,)(pg, op1, op2, op3);
558 }
559
test_svmad_n_f16_z(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)560 svfloat16_t test_svmad_n_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
561 {
562 // CHECK-LABEL: test_svmad_n_f16_z
563 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
564 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
565 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
566 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
567 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
568 return SVE_ACLE_FUNC(svmad,_n_f16,_z,)(pg, op1, op2, op3);
569 }
570
test_svmad_n_f32_z(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)571 svfloat32_t test_svmad_n_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
572 {
573 // CHECK-LABEL: test_svmad_n_f32_z
574 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
575 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
576 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
577 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
578 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
579 return SVE_ACLE_FUNC(svmad,_n_f32,_z,)(pg, op1, op2, op3);
580 }
581
test_svmad_n_f64_z(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)582 svfloat64_t test_svmad_n_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
583 {
584 // CHECK-LABEL: test_svmad_n_f64_z
585 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
586 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
587 // CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
588 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
589 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
590 return SVE_ACLE_FUNC(svmad,_n_f64,_z,)(pg, op1, op2, op3);
591 }
592
test_svmad_n_f16_m(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)593 svfloat16_t test_svmad_n_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
594 {
595 // CHECK-LABEL: test_svmad_n_f16_m
596 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
597 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
598 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
599 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
600 return SVE_ACLE_FUNC(svmad,_n_f16,_m,)(pg, op1, op2, op3);
601 }
602
test_svmad_n_f32_m(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)603 svfloat32_t test_svmad_n_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
604 {
605 // CHECK-LABEL: test_svmad_n_f32_m
606 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
607 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
608 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
609 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
610 return SVE_ACLE_FUNC(svmad,_n_f32,_m,)(pg, op1, op2, op3);
611 }
612
test_svmad_n_f64_m(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)613 svfloat64_t test_svmad_n_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
614 {
615 // CHECK-LABEL: test_svmad_n_f64_m
616 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
617 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
618 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
619 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
620 return SVE_ACLE_FUNC(svmad,_n_f64,_m,)(pg, op1, op2, op3);
621 }
622
test_svmad_n_f16_x(svbool_t pg,svfloat16_t op1,svfloat16_t op2,float16_t op3)623 svfloat16_t test_svmad_n_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, float16_t op3)
624 {
625 // CHECK-LABEL: test_svmad_n_f16_x
626 // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
627 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op3)
628 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2, <vscale x 8 x half> %[[DUP]])
629 // CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
630 return SVE_ACLE_FUNC(svmad,_n_f16,_x,)(pg, op1, op2, op3);
631 }
632
test_svmad_n_f32_x(svbool_t pg,svfloat32_t op1,svfloat32_t op2,float32_t op3)633 svfloat32_t test_svmad_n_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, float32_t op3)
634 {
635 // CHECK-LABEL: test_svmad_n_f32_x
636 // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
637 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op3)
638 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2, <vscale x 4 x float> %[[DUP]])
639 // CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
640 return SVE_ACLE_FUNC(svmad,_n_f32,_x,)(pg, op1, op2, op3);
641 }
642
test_svmad_n_f64_x(svbool_t pg,svfloat64_t op1,svfloat64_t op2,float64_t op3)643 svfloat64_t test_svmad_n_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, float64_t op3)
644 {
645 // CHECK-LABEL: test_svmad_n_f64_x
646 // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
647 // CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op3)
648 // CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fmad.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2, <vscale x 2 x double> %[[DUP]])
649 // CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
650 return SVE_ACLE_FUNC(svmad,_n_f64,_x,)(pg, op1, op2, op3);
651 }
652