1 //===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #if defined(__arm64__) || defined(__aarch64__) 10 11 #ifndef lldb_NativeRegisterContextLinux_arm64_h 12 #define lldb_NativeRegisterContextLinux_arm64_h 13 14 #include "Plugins/Process/Linux/NativeRegisterContextLinux.h" 15 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 16 17 #include <asm/ptrace.h> 18 19 namespace lldb_private { 20 namespace process_linux { 21 22 class NativeProcessLinux; 23 24 class NativeRegisterContextLinux_arm64 : public NativeRegisterContextLinux { 25 public: 26 NativeRegisterContextLinux_arm64(const ArchSpec &target_arch, 27 NativeThreadProtocol &native_thread); 28 29 uint32_t GetRegisterSetCount() const override; 30 31 uint32_t GetUserRegisterCount() const override; 32 33 const RegisterSet *GetRegisterSet(uint32_t set_index) const override; 34 35 Status ReadRegister(const RegisterInfo *reg_info, 36 RegisterValue ®_value) override; 37 38 Status WriteRegister(const RegisterInfo *reg_info, 39 const RegisterValue ®_value) override; 40 41 Status ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override; 42 43 Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override; 44 45 void InvalidateAllRegisters() override; 46 47 // Hardware breakpoints/watchpoint management functions 48 49 uint32_t NumSupportedHardwareBreakpoints() override; 50 51 uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override; 52 53 bool ClearHardwareBreakpoint(uint32_t hw_idx) override; 54 55 Status ClearAllHardwareBreakpoints() override; 56 57 Status GetHardwareBreakHitIndex(uint32_t &bp_index, 58 lldb::addr_t trap_addr) override; 59 60 uint32_t NumSupportedHardwareWatchpoints() override; 61 62 uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size, 63 uint32_t watch_flags) override; 64 65 bool ClearHardwareWatchpoint(uint32_t hw_index) override; 66 67 Status ClearAllHardwareWatchpoints() override; 68 69 Status GetWatchpointHitIndex(uint32_t &wp_index, 70 lldb::addr_t trap_addr) override; 71 72 lldb::addr_t GetWatchpointHitAddress(uint32_t wp_index) override; 73 74 lldb::addr_t GetWatchpointAddress(uint32_t wp_index) override; 75 76 uint32_t GetWatchpointSize(uint32_t wp_index); 77 78 bool WatchpointIsEnabled(uint32_t wp_index); 79 80 // Debug register type select 81 enum DREGType { eDREGTypeWATCH = 0, eDREGTypeBREAK }; 82 83 protected: 84 85 Status ReadGPR() override; 86 87 Status WriteGPR() override; 88 89 Status ReadFPR() override; 90 91 Status WriteFPR() override; 92 GetGPRBuffer()93 void *GetGPRBuffer() override { return &m_gpr_arm64; } 94 GetFPRBuffer()95 void *GetFPRBuffer() override { return &m_fpr; } 96 GetFPRSize()97 size_t GetFPRSize() override { return sizeof(m_fpr); } 98 99 private: 100 bool m_gpr_is_valid; 101 bool m_fpu_is_valid; 102 bool m_sve_buffer_is_valid; 103 104 bool m_sve_header_is_valid; 105 106 RegisterInfoPOSIX_arm64::GPR m_gpr_arm64; // 64-bit general purpose registers. 107 108 RegisterInfoPOSIX_arm64::FPU 109 m_fpr; // floating-point registers including extended register sets. 110 111 SVEState m_sve_state; 112 struct user_sve_header m_sve_header; 113 std::vector<uint8_t> m_sve_ptrace_payload; 114 115 // Debug register info for hardware breakpoints and watchpoints management. 116 struct DREG { 117 lldb::addr_t address; // Breakpoint/watchpoint address value. 118 lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception 119 // occurred. 120 lldb::addr_t real_addr; // Address value that should cause target to stop. 121 uint32_t control; // Breakpoint/watchpoint control value. 122 uint32_t refcount; // Serves as enable/disable and reference counter. 123 }; 124 125 struct DREG m_hbr_regs[16]; // Arm native linux hardware breakpoints 126 struct DREG m_hwp_regs[16]; // Arm native linux hardware watchpoints 127 128 uint32_t m_max_hwp_supported; 129 uint32_t m_max_hbp_supported; 130 bool m_refresh_hwdebug_info; 131 132 bool IsGPR(unsigned reg) const; 133 134 bool IsFPR(unsigned reg) const; 135 136 Status ReadAllSVE(); 137 138 Status WriteAllSVE(); 139 140 Status ReadSVEHeader(); 141 142 Status WriteSVEHeader(); 143 144 bool IsSVE(unsigned reg) const; 145 GetSVERegVG()146 uint64_t GetSVERegVG() { return m_sve_header.vl / 8; } 147 SetSVERegVG(uint64_t vg)148 void SetSVERegVG(uint64_t vg) { m_sve_header.vl = vg * 8; } 149 GetSVEHeader()150 void *GetSVEHeader() { return &m_sve_header; } 151 152 void *GetSVEBuffer(); 153 GetSVEHeaderSize()154 size_t GetSVEHeaderSize() { return sizeof(m_sve_header); } 155 GetSVEBufferSize()156 size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); } 157 158 Status ReadHardwareDebugInfo(); 159 160 Status WriteHardwareDebugRegs(int hwbType); 161 162 uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const; 163 164 RegisterInfoPOSIX_arm64 &GetRegisterInfo() const; 165 166 void ConfigureRegisterContext(); 167 168 uint32_t CalculateSVEOffset(const RegisterInfo *reg_info) const; 169 }; 170 171 } // namespace process_linux 172 } // namespace lldb_private 173 174 #endif // #ifndef lldb_NativeRegisterContextLinux_arm64_h 175 176 #endif // defined (__arm64__) || defined (__aarch64__) 177