1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11
12 #include "SparcTargetMachine.h"
13 #include "LeonPasses.h"
14 #include "Sparc.h"
15 #include "SparcTargetObjectFile.h"
16 #include "TargetInfo/SparcTargetInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h"
21 using namespace llvm;
22
LLVMInitializeSparcTarget()23 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() {
24 // Register the target.
25 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
26 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
27 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
28 }
29
computeDataLayout(const Triple & T,bool is64Bit)30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
31 // Sparc is typically big endian, but some are little.
32 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
33 Ret += "-m:e";
34
35 // Some ABIs have 32bit pointers.
36 if (!is64Bit)
37 Ret += "-p:32:32";
38
39 // Alignments for 64 bit integers.
40 Ret += "-i64:64";
41
42 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
43 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
44 if (is64Bit)
45 Ret += "-n32:64";
46 else
47 Ret += "-f128:64-n32";
48
49 if (is64Bit)
50 Ret += "-S128";
51 else
52 Ret += "-S64";
53
54 return Ret;
55 }
56
getEffectiveRelocModel(Optional<Reloc::Model> RM)57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
58 if (!RM.hasValue())
59 return Reloc::Static;
60 return *RM;
61 }
62
63 // Code models. Some only make sense for 64-bit code.
64 //
65 // SunCC Reloc CodeModel Constraints
66 // abs32 Static Small text+data+bss linked below 2^32 bytes
67 // abs44 Static Medium text+data+bss linked below 2^44 bytes
68 // abs64 Static Large text smaller than 2^31 bytes
69 // pic13 PIC_ Small GOT < 2^13 bytes
70 // pic32 PIC_ Medium GOT < 2^32 bytes
71 //
72 // All code models require that the text segment is smaller than 2GB.
73 static CodeModel::Model
getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM,Reloc::Model RM,bool Is64Bit,bool JIT)74 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
75 bool Is64Bit, bool JIT) {
76 if (CM) {
77 if (*CM == CodeModel::Tiny)
78 report_fatal_error("Target does not support the tiny CodeModel", false);
79 if (*CM == CodeModel::Kernel)
80 report_fatal_error("Target does not support the kernel CodeModel", false);
81 return *CM;
82 }
83 if (Is64Bit) {
84 if (JIT)
85 return CodeModel::Large;
86 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
87 }
88 return CodeModel::Small;
89 }
90
91 /// Create an ILP32 architecture model
SparcTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT,bool is64bit)92 SparcTargetMachine::SparcTargetMachine(
93 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
94 const TargetOptions &Options, Optional<Reloc::Model> RM,
95 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
96 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
97 getEffectiveRelocModel(RM),
98 getEffectiveSparcCodeModel(
99 CM, getEffectiveRelocModel(RM), is64bit, JIT),
100 OL),
101 TLOF(std::make_unique<SparcELFTargetObjectFile>()),
102 Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit),
103 is64Bit(is64bit) {
104 initAsmInfo();
105 }
106
~SparcTargetMachine()107 SparcTargetMachine::~SparcTargetMachine() {}
108
109 const SparcSubtarget *
getSubtargetImpl(const Function & F) const110 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
111 Attribute CPUAttr = F.getFnAttribute("target-cpu");
112 Attribute FSAttr = F.getFnAttribute("target-features");
113
114 std::string CPU =
115 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
116 std::string FS =
117 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
118
119 // FIXME: This is related to the code below to reset the target options,
120 // we need to know whether or not the soft float flag is set on the
121 // function, so we can enable it as a subtarget feature.
122 bool softFloat =
123 F.hasFnAttribute("use-soft-float") &&
124 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
125
126 if (softFloat)
127 FS += FS.empty() ? "+soft-float" : ",+soft-float";
128
129 auto &I = SubtargetMap[CPU + FS];
130 if (!I) {
131 // This needs to be done before we create a new subtarget since any
132 // creation will depend on the TM and the code generation flags on the
133 // function that reside in TargetOptions.
134 resetTargetOptions(F);
135 I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
136 this->is64Bit);
137 }
138 return I.get();
139 }
140
141 namespace {
142 /// Sparc Code Generator Pass Configuration Options.
143 class SparcPassConfig : public TargetPassConfig {
144 public:
SparcPassConfig(SparcTargetMachine & TM,PassManagerBase & PM)145 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
146 : TargetPassConfig(TM, PM) {}
147
getSparcTargetMachine() const148 SparcTargetMachine &getSparcTargetMachine() const {
149 return getTM<SparcTargetMachine>();
150 }
151
152 void addIRPasses() override;
153 bool addInstSelector() override;
154 void addPreEmitPass() override;
155 };
156 } // namespace
157
createPassConfig(PassManagerBase & PM)158 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
159 return new SparcPassConfig(*this, PM);
160 }
161
addIRPasses()162 void SparcPassConfig::addIRPasses() {
163 addPass(createAtomicExpandPass());
164
165 TargetPassConfig::addIRPasses();
166 }
167
addInstSelector()168 bool SparcPassConfig::addInstSelector() {
169 addPass(createSparcISelDag(getSparcTargetMachine()));
170 return false;
171 }
172
addPreEmitPass()173 void SparcPassConfig::addPreEmitPass(){
174 addPass(createSparcDelaySlotFillerPass());
175
176 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
177 {
178 addPass(new InsertNOPLoad());
179 }
180 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
181 addPass(new DetectRoundChange());
182 }
183 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
184 {
185 addPass(new FixAllFDIVSQRT());
186 }
187 }
188
anchor()189 void SparcV8TargetMachine::anchor() { }
190
SparcV8TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)191 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
192 StringRef CPU, StringRef FS,
193 const TargetOptions &Options,
194 Optional<Reloc::Model> RM,
195 Optional<CodeModel::Model> CM,
196 CodeGenOpt::Level OL, bool JIT)
197 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
198
anchor()199 void SparcV9TargetMachine::anchor() { }
200
SparcV9TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)201 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
202 StringRef CPU, StringRef FS,
203 const TargetOptions &Options,
204 Optional<Reloc::Model> RM,
205 Optional<CodeModel::Model> CM,
206 CodeGenOpt::Level OL, bool JIT)
207 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
208
anchor()209 void SparcelTargetMachine::anchor() {}
210
SparcelTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)211 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
212 StringRef CPU, StringRef FS,
213 const TargetOptions &Options,
214 Optional<Reloc::Model> RM,
215 Optional<CodeModel::Model> CM,
216 CodeGenOpt::Level OL, bool JIT)
217 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
218