1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -verify-machineinstrs -o - %s | FileCheck %s
3
4define i32 @test_sgpr_reg_class_constraint() nounwind {
5; CHECK-LABEL: test_sgpr_reg_class_constraint:
6; CHECK:       ; %bb.0: ; %entry
7; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; CHECK-NEXT:    ;;#ASMSTART
9; CHECK-NEXT:    s_mov_b32 s4, 7
10; CHECK-NEXT:    ;;#ASMEND
11; CHECK-NEXT:    ;;#ASMSTART
12; CHECK-NEXT:    s_mov_b32 s5, 8
13; CHECK-NEXT:    ;;#ASMEND
14; CHECK-NEXT:    ;;#ASMSTART
15; CHECK-NEXT:    s_add_u32 s4, s4, s5
16; CHECK-NEXT:    ;;#ASMEND
17; CHECK-NEXT:    v_mov_b32_e32 v0, s4
18; CHECK-NEXT:    s_setpc_b64 s[30:31]
19entry:
20  %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
21  %asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
22  %asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,s"(i32 %asm0, i32 %asm1) nounwind
23  ret i32 %asm2
24}
25
26define i32 @test_sgpr_matching_constraint() nounwind {
27; CHECK-LABEL: test_sgpr_matching_constraint:
28; CHECK:       ; %bb.0: ; %entry
29; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
30; CHECK-NEXT:    ;;#ASMSTART
31; CHECK-NEXT:    s_mov_b32 s5, 7
32; CHECK-NEXT:    ;;#ASMEND
33; CHECK-NEXT:    ;;#ASMSTART
34; CHECK-NEXT:    s_mov_b32 s4, 8
35; CHECK-NEXT:    ;;#ASMEND
36; CHECK-NEXT:    ;;#ASMSTART
37; CHECK-NEXT:    s_add_u32 s4, s5, s4
38; CHECK-NEXT:    ;;#ASMEND
39; CHECK-NEXT:    v_mov_b32_e32 v0, s4
40; CHECK-NEXT:    s_setpc_b64 s[30:31]
41entry:
42  %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
43  %asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind
44  %asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,0"(i32 %asm0, i32 %asm1) nounwind
45  ret i32 %asm2
46}
47
48define i32 @test_sgpr_to_vgpr_move_reg_class_constraint() nounwind {
49; CHECK-LABEL: test_sgpr_to_vgpr_move_reg_class_constraint:
50; CHECK:       ; %bb.0: ; %entry
51; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
52; CHECK-NEXT:    ;;#ASMSTART
53; CHECK-NEXT:    s_mov_b32 s4, 7
54; CHECK-NEXT:    ;;#ASMEND
55; CHECK-NEXT:    ;;#ASMSTART
56; CHECK-NEXT:    v_mov_b32 v0, s4
57; CHECK-NEXT:    ;;#ASMEND
58; CHECK-NEXT:    s_setpc_b64 s[30:31]
59entry:
60  %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
61  %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,s"(i32 %asm0) nounwind
62  ret i32 %asm1
63}
64
65define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {
66; CHECK-LABEL: test_sgpr_to_vgpr_move_matching_constraint:
67; CHECK:       ; %bb.0: ; %entry
68; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
69; CHECK-NEXT:    ;;#ASMSTART
70; CHECK-NEXT:    s_mov_b32 s4, 7
71; CHECK-NEXT:    ;;#ASMEND
72; CHECK-NEXT:    v_mov_b32_e32 v0, s4
73; CHECK-NEXT:    ;;#ASMSTART
74; CHECK-NEXT:    v_mov_b32 v0, v0
75; CHECK-NEXT:    ;;#ASMEND
76; CHECK-NEXT:    s_setpc_b64 s[30:31]
77entry:
78  %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind
79  %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind
80  ret i32 %asm1
81}
82
83!0 = !{i32 70}
84