1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
5
6---
7name: fabs_s32_ss
8legalized: true
9regBankSelected: true
10tracksRegLiveness: true
11
12body: |
13  bb.0:
14    liveins: $sgpr0
15    ; GCN-LABEL: name: fabs_s32_ss
16    ; GCN: liveins: $sgpr0
17    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
18    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
19    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
20    ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
21    %0:sgpr(s32) = COPY $sgpr0
22    %1:sgpr(s32) = G_FABS %0
23    $sgpr0 = COPY %1
24...
25
26---
27name: fabs_s32_vv
28legalized: true
29regBankSelected: true
30tracksRegLiveness: true
31
32body: |
33  bb.0:
34    liveins: $vgpr0
35    ; GCN-LABEL: name: fabs_s32_vv
36    ; GCN: liveins: $vgpr0
37    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
38    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
39    ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
40    ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
41    %0:vgpr(s32) = COPY $vgpr0
42    %1:vgpr(s32) = G_FABS %0
43    $vgpr0 = COPY %1
44...
45
46---
47name: fabs_s32_vs
48legalized: true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $sgpr0
55    ; GCN-LABEL: name: fabs_s32_vs
56    ; GCN: liveins: $sgpr0
57    ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
58    ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
59    ; GCN: $vgpr0 = COPY [[FABS]](s32)
60    %0:sgpr(s32) = COPY $sgpr0
61    %1:vgpr(s32) = G_FABS %0
62    $vgpr0 = COPY %1
63...
64
65---
66name: fabs_v2s16_ss
67legalized: true
68regBankSelected: true
69tracksRegLiveness: true
70
71body: |
72  bb.0:
73    liveins: $sgpr0_sgpr1
74    ; GCN-LABEL: name: fabs_v2s16_ss
75    ; GCN: liveins: $sgpr0_sgpr1
76    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
77    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
78    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
79    ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
80    %0:sgpr(<2 x s16>) = COPY $sgpr0
81    %1:sgpr(<2 x s16>) = G_FABS %0
82    $sgpr0 = COPY %1
83...
84
85---
86name: fabs_s16_ss
87legalized: true
88regBankSelected: true
89tracksRegLiveness: true
90
91body: |
92  bb.0:
93    liveins: $sgpr0
94    ; GCN-LABEL: name: fabs_s16_ss
95    ; GCN: liveins: $sgpr0
96    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
97    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
98    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
99    ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
100    %0:sgpr(s32) = COPY $sgpr0
101    %1:sgpr(s16) = G_TRUNC %0
102    %2:sgpr(s16) = G_FABS %1
103    %3:sgpr(s32) = G_ANYEXT %2
104    $sgpr0 = COPY %3
105...
106
107---
108name: fabs_s16_vv
109legalized: true
110regBankSelected: true
111tracksRegLiveness: true
112
113body: |
114  bb.0:
115    liveins: $vgpr0
116    ; GCN-LABEL: name: fabs_s16_vv
117    ; GCN: liveins: $vgpr0
118    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
119    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
120    ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
121    ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
122    %0:vgpr(s32) = COPY $vgpr0
123    %1:vgpr(s16) = G_TRUNC %0
124    %2:vgpr(s16) = G_FABS %1
125    %3:vgpr(s32) = G_ANYEXT %2
126    $vgpr0 = COPY %3
127...
128
129---
130name: fabs_s16_vs
131legalized: true
132regBankSelected: true
133tracksRegLiveness: true
134
135body: |
136  bb.0:
137    liveins: $sgpr0
138
139    ; GCN-LABEL: name: fabs_s16_vs
140    ; GCN: liveins: $sgpr0
141    ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
142    ; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
143    ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
144    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
145    ; GCN: $vgpr0 = COPY [[COPY1]](s32)
146    %0:sgpr(s32) = COPY $sgpr0
147    %1:sgpr(s16) = G_TRUNC %0
148    %2:vgpr(s16) = G_FABS %1
149    %3:vgpr(s32) = G_ANYEXT %2
150    $vgpr0 = COPY %3
151...
152
153---
154name: fabs_v2s16_vv
155legalized: true
156regBankSelected: true
157tracksRegLiveness: true
158
159body: |
160  bb.0:
161    liveins: $vgpr0
162    ; GCN-LABEL: name: fabs_v2s16_vv
163    ; GCN: liveins: $vgpr0
164    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
165    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
166    ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
167    ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
168    %0:vgpr(<2 x s16>) = COPY $vgpr0
169    %1:vgpr(<2 x s16>) = G_FABS %0
170    $vgpr0 = COPY %1
171...
172
173---
174name: fabs_v2s16_vs
175legalized: true
176regBankSelected: true
177tracksRegLiveness: true
178
179body: |
180  bb.0:
181    liveins: $sgpr0
182    ; GCN-LABEL: name: fabs_v2s16_vs
183    ; GCN: liveins: $sgpr0
184    ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
185    ; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
186    ; GCN: $vgpr0 = COPY [[FABS]](<2 x s16>)
187    %0:sgpr(<2 x s16>) = COPY $sgpr0
188    %1:vgpr(<2 x s16>) = G_FABS %0
189    $vgpr0 = COPY %1
190...
191
192---
193name: fabs_s64_ss
194legalized: true
195regBankSelected: true
196tracksRegLiveness: true
197
198body: |
199  bb.0:
200    liveins: $sgpr0_sgpr1
201    ; GCN-LABEL: name: fabs_s64_ss
202    ; GCN: liveins: $sgpr0_sgpr1
203    ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
204    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
205    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
206    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
207    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
208    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
209    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
210    %0:sgpr(s64) = COPY $sgpr0_sgpr1
211    %1:sgpr(s64) = G_FABS %0
212    S_ENDPGM 0, implicit %1
213...
214
215---
216name: fabs_s64_vv
217legalized: true
218regBankSelected: true
219tracksRegLiveness: true
220
221body: |
222  bb.0:
223    liveins: $vgpr0_vgpr1
224    ; GCN-LABEL: name: fabs_s64_vv
225    ; GCN: liveins: $vgpr0_vgpr1
226    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
227    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
228    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
229    ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
230    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
231    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
232    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
233    %0:vgpr(s64) = COPY $vgpr0_vgpr1
234    %1:vgpr(s64) = G_FABS %0
235    S_ENDPGM 0, implicit %1
236...
237
238---
239name: fabs_s64_vs
240legalized: true
241regBankSelected: true
242tracksRegLiveness: true
243
244body: |
245  bb.0:
246    liveins: $sgpr0_sgpr1
247    ; GCN-LABEL: name: fabs_s64_vs
248    ; GCN: liveins: $sgpr0_sgpr1
249    ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
250    ; GCN: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
251    ; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
252    %0:sgpr(s64) = COPY $sgpr0_sgpr1
253    %1:vgpr(s64) = G_FABS %0
254    S_ENDPGM 0, implicit %1
255...
256
257# Make sure the source register is constrained
258---
259name: fabs_s64_vv_no_src_constraint
260legalized: true
261regBankSelected: true
262tracksRegLiveness: true
263
264body: |
265  bb.0:
266    liveins: $vgpr0_vgpr1
267    ; GCN-LABEL: name: fabs_s64_vv_no_src_constraint
268    ; GCN: liveins: $vgpr0_vgpr1
269    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
270    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
271    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
272    ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
273    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
274    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
275    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
276    %0:vgpr(s64) = IMPLICIT_DEF
277    %1:vgpr(s64) = G_FABS %0:vgpr(s64)
278    S_ENDPGM 0, implicit %1
279...
280
281---
282name: fabs_s64_ss_no_src_constraint
283legalized: true
284regBankSelected: true
285tracksRegLiveness: true
286
287body: |
288  bb.0:
289    liveins: $sgpr0_sgpr1
290    ; GCN-LABEL: name: fabs_s64_ss_no_src_constraint
291    ; GCN: liveins: $sgpr0_sgpr1
292    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
293    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
294    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
295    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
296    ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
297    ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
298    ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
299    %0:sgpr(s64) = IMPLICIT_DEF
300    %1:sgpr(s64) = G_FABS %0:sgpr(s64)
301    S_ENDPGM 0, implicit %1
302...
303